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OMAP3: Remove legacy NAND defines
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Remove remaining legacy NAND defines for Beagle, EVM, Overo and Pandora.

Signed-off-by: Dirk Behme <[email protected]>
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@dirkbehme @plagnioj
dirkbehme authored and plagnioj committed Apr 29, 2009
1 parent cba0b77 commit 42bf4b2
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Showing 4 changed files with 0 additions and 117 deletions.
29 changes: 0 additions & 29 deletions include/configs/omap3_beagle.h
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Original file line number Diff line number Diff line change
Expand Up @@ -141,18 +141,6 @@

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512

#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
Expand Down Expand Up @@ -312,21 +300,4 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif


#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)

/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)

#endif /* __CONFIG_H */
29 changes: 0 additions & 29 deletions include/configs/omap3_evm.h
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Expand Up @@ -138,18 +138,6 @@

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define SECTORSIZE 512

#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
Expand Down Expand Up @@ -304,23 +292,6 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif


#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)

/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)

/*----------------------------------------------------------------------------
* SMSC9115 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
Expand Down
30 changes: 0 additions & 30 deletions include/configs/omap3_overo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -128,19 +128,6 @@

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512

#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
Expand Down Expand Up @@ -299,21 +286,4 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif


#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)

/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)

#endif /* __CONFIG_H */
29 changes: 0 additions & 29 deletions include/configs/omap3_pandora.h
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Original file line number Diff line number Diff line change
Expand Up @@ -131,18 +131,6 @@

#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define SECTORSIZE 512

#define NAND_ALLOW_ERASE_ALL
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_NO_RB 1
#define CONFIG_SYS_NAND_WP

#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
Expand Down Expand Up @@ -301,21 +289,4 @@ extern unsigned int boot_flash_sec;
extern unsigned int boot_flash_type;
#endif


#define WRITE_NAND_COMMAND(d, adr)\
writel(d, &nand_cs_base->nand_cmd)
#define WRITE_NAND_ADDRESS(d, adr)\
writel(d, &nand_cs_base->nand_adr)
#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)

/* Other NAND Access APIs */
#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
while (0)
#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
while (0)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define NAND_WAIT_READY(nand) udelay(10)

#endif /* __CONFIG_H */

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