x86: irq: Fix some typos

Fix some typos in arch/x86/include/asm/irq.h. Signed-off-by: Wolfgang Wallner <[email protected]> Reviewed-by: Bin Meng <[email protected]>
imaami · Aug 3, 2020 · 4911358 · 4911358
1 parent a2d051e
commit 4911358
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
@@ -12,8 +12,8 @@
  * Intel interrupt router configuration mechanism
  *
  * There are two known ways of Intel interrupt router configuration mechanism
- * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
- * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
+ * so far. On most cases, the IRQ routing configuration is controlled by PCI
+ * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0).
  * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
  * in the IBASE register block where IBASE is memory-mapped.
  */
@@ -36,7 +36,7 @@ struct pirq_regmap {
  * @link_base:	link value base number
  * @link_num:	number of PIRQ links supported
  * @has_regmap:	has mapping table between PIRQ link and routing register offset
- * @irq_mask:	IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
+ * @irq_mask:	IRQ mask representing the 16 IRQs in 8259, bit N is 1 means
  *		IRQ N is available to be routed
  * @lb_bdf:	irq router's PCI bus/device/function number encoding
  * @ibase:	IBASE register block base address