Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
imaami · Apr 22, 2023 · 802132c · 802132c
2 parents da142d1 + 04d16be
commit 802132c
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Showing 66 changed files with 8,456 additions and 58 deletions.
diff --git a/Makefile b/Makefile
@@ -1761,7 +1761,7 @@ ifeq ($(CONFIG_KALLSYMS),y)
 endif
 
 ifeq ($(CONFIG_RISCV),y)
-	@tools/prelink-riscv $@ 0
+	@tools/prelink-riscv $@
 endif
 
 quiet_cmd_sym ?= SYM     $@

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
@@ -24,6 +24,9 @@ config TARGET_SIFIVE_UNMATCHED
 	bool "Support SiFive Unmatched Board"
 	select SYS_CACHE_SHIFT_6
 
+config TARGET_STARFIVE_VISIONFIVE2
+	bool "Support StarFive VisionFive2 Board"
+
 config TARGET_SIPEED_MAIX
 	bool "Support Sipeed Maix Board"
 	select SYS_CACHE_SHIFT_6
@@ -65,12 +68,14 @@ source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
 source "board/sipeed/maix/Kconfig"
+source "board/starfive/visionfive2/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/andesv5/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
+source "arch/riscv/cpu/jh7110/Kconfig"
 
 # architecture-specific options below
 

diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
@@ -16,16 +16,17 @@
 ifdef CONFIG_32BIT
 KBUILD_LDFLAGS		+= -m $(32bit-emul)
 EFI_LDS			:= elf_riscv32_efi.lds
+PLATFORM_ELFFLAGS	+= -B riscv -O elf32-littleriscv
 endif
 
 ifdef CONFIG_64BIT
 KBUILD_LDFLAGS		+= -m $(64bit-emul)
 EFI_LDS			:= elf_riscv64_efi.lds
+PLATFORM_ELFFLAGS	+= -B riscv -O elf64-littleriscv
 endif
 
 PLATFORM_CPPFLAGS	+= -ffixed-gp -fpic
-PLATFORM_RELFLAGS	+= -fno-common -gdwarf-2 -ffunction-sections \
-			   -fdata-sections
+PLATFORM_RELFLAGS	+= -fno-common -ffunction-sections -fdata-sections
 LDFLAGS_u-boot		+= --gc-sections -static -pie
 
 EFI_CRT0		:= crt0_riscv_efi.o

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+config STARFIVE_JH7110
+	bool
+	select ARCH_EARLY_INIT_R
+	select CLK_JH7110
+	select CPU
+	select CPU_RISCV
+	select RAM
+	select RESET_JH7110
+	select SUPPORT_SPL
+	select SPL_RAM if SPL
+	select SPL_STARFIVE_DDR
+	select PINCTRL_STARFIVE_JH7110
+	imply MMC
+	imply MMC_BROKEN_CD
+	imply MMC_SPI
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SIFIVE_CACHE
+	imply SIFIVE_CCACHE
+	imply SMP
+	imply SPI
+	imply SPL_CPU
+	imply SPL_LOAD_FIT
+	imply SPL_OPENSBI
+	imply SPL_SIFIVE_CLINT
diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <[email protected]>
+ */
+
+#include <asm/cache.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <[email protected]>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+		return SZ_4G;
+
+	return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<[email protected]>
+ */
+
+#include <asm/csr.h>
+#include <asm/sections.h>
+#include <dm.h>
+#include <log.h>
+
+#define CSR_U74_FEATURE_DISABLE	0x7c1
+#define L2_LIM_MEM_END	0x81FFFFFUL
+
+int spl_soc_init(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* DDR init */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+void harts_early_init(void)
+{
+	ulong *ptr;
+	u8 *tmp;
+	ulong len, remain;
+	/*
+	 * Feature Disable CSR
+	 *
+	 * Clear feature disable CSR to '0' to turn on all features for
+	 * each core. This operation must be in M-mode.
+	 */
+	if (CONFIG_IS_ENABLED(RISCV_MMODE))
+		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+	/* clear L2 LIM  memory
+	 * set __bss_end to 0x81FFFFF region to zero
+	 * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
+	 * If it is not cleared, the ECC part is invalid, and an ECC error
+	 * will be reported when reading data.
+	 */
+	ptr = (ulong *)&__bss_end;
+	len = L2_LIM_MEM_END - (ulong)&__bss_end;
+	remain = len % sizeof(ulong);
+	len /= sizeof(ulong);
+
+	while (len--)
+		*ptr++ = 0;
+
+	/* clear the remain bytes */
+	if (remain) {
+		tmp = (u8 *)ptr;
+		while (remain--)
+			*tmp++ = 0;
+	}
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
@@ -250,9 +250,10 @@ spl_secondary_hart_stack_gd_setup:
 spl_call_board_init_r:
 	mv	a0, zero
 	mv	a1, zero
-	jal	board_init_r
+	j	board_init_r
 #endif
 
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * void relocate_code(addr_sp, gd, addr_moni)
  *
@@ -283,9 +284,7 @@ stack_setup:
 	beq	t0, s4, clear_bss	/* skip relocation */
 
 	mv	t1, s4			/* t1 <- scratch for copy_loop */
-	la	t3, __bss_start
-	sub	t3, t3, t0		/* t3 <- __bss_start_ofs */
-	add	t2, t0, t3		/* t2 <- source end address */
+	la	t2, __bss_start		/* t2 <- source end address */
 
 copy_loop:
 	LREG	t5, 0(t0)
@@ -304,17 +303,12 @@ fix_rela_dyn:
 	add	t1, t1, t6		/* t1 <- rela_dyn_start in RAM */
 	add	t2, t2, t6		/* t2 <- rela_dyn_end in RAM */
 
-/*
- * skip first reserved entry: address, type, addend
- */
-	j	10f
-
 6:
-	LREG	t5, -(REGBYTES*2)(t1)	/* t5 <-- relocation info:type */
+	LREG	t5, REGBYTES(t1)	/* t5 <-- relocation info:type */
 	li	t3, R_RISCV_RELATIVE	/* reloc type R_RISCV_RELATIVE */
 	bne	t5, t3, 8f		/* skip non-RISCV_RELOC entries */
-	LREG	t3, -(REGBYTES*3)(t1)
-	LREG	t5, -(REGBYTES)(t1)	/* t5 <-- addend */
+	LREG	t3, 0(t1)
+	LREG	t5, (REGBYTES * 2)(t1)	/* t5 <-- addend */
 	add	t5, t5, t6		/* t5 <-- location to fix up in RAM */
 	add	t3, t3, t6		/* t3 <-- location to fix up in RAM */
 	SREG	t5, 0(t3)
@@ -325,25 +319,24 @@ fix_rela_dyn:
 	add	t4, t4, t6
 
 9:
-	LREG	t5, -(REGBYTES*2)(t1)	/* t5 <-- relocation info:type */
 	srli	t0, t5, SYM_INDEX	/* t0 <--- sym table index */
 	andi	t5, t5, 0xFF		/* t5 <--- relocation type */
 	li	t3, RELOC_TYPE
 	bne	t5, t3, 10f		/* skip non-addned entries */
 
-	LREG	t3, -(REGBYTES*3)(t1)
+	LREG	t3, 0(t1)
 	li	t5, SYM_SIZE
 	mul	t0, t0, t5
 	add	s5, t4, t0
-	LREG	t0, -(REGBYTES)(t1)	/* t0 <-- addend */
+	LREG	t0, (REGBYTES * 2)(t1)	/* t0 <-- addend */
 	LREG	t5, REGBYTES(s5)
 	add	t5, t5, t0
 	add	t5, t5, t6		/* t5 <-- location to fix up in RAM */
 	add	t3, t3, t6		/* t3 <-- location to fix up in RAM */
 	SREG	t5, 0(t3)
 10:
-	addi	t1, t1, (REGBYTES*3)
-	ble	t1, t2, 6b
+	addi	t1, t1, (REGBYTES * 3)
+	blt	t1, t2, 6b
 
 /*
  * trap update
@@ -408,6 +401,7 @@ call_board_init_r:
  * jump to it ...
  */
 	jr	t4			/* jump to board_init_r() */
+#endif /* !defined(CONFIG_SPL_BUILD) */
 
 #if CONFIG_IS_ENABLED(SMP)
 hart_out_of_bounds_loop:

diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
@@ -32,14 +32,6 @@ SECTIONS
 	} > .spl_mem
 	. = ALIGN(4);
 
-	.got : {
-		__got_start = .;
-		*(.got.plt) *(.got)
-		__got_end = .;
-	} > .spl_mem
-
-	. = ALIGN(4);
-
 	__u_boot_list : {
 		KEEP(*(SORT(__u_boot_list*)));
 	} > .spl_mem
@@ -52,24 +44,7 @@ SECTIONS
 		__binman_sym_end = .;
 	} > .spl_mem
 
-	. = ALIGN(4);
-
-	/DISCARD/ : { *(.rela.plt*) }
-	.rela.dyn : {
-		__rel_dyn_start = .;
-		*(.rela*)
-		__rel_dyn_end = .;
-	} > .spl_mem
-
-	. = ALIGN(4);
-
-	.dynsym : {
-		__dyn_sym_start = .;
-		*(.dynsym)
-		__dyn_sym_end = .;
-	} > .spl_mem
-
-	. = ALIGN(4);
+	. = ALIGN(8);
 
 	_end = .;
 	_image_binary_end = .;

diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
@@ -57,7 +57,7 @@ SECTIONS
 		__efi_runtime_rel_stop = .;
 	}
 
-	. = ALIGN(4);
+	. = ALIGN(8);
 
 	/DISCARD/ : { *(.rela.plt*) }
 	.rela.dyn : {
@@ -66,15 +66,15 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
-	. = ALIGN(4);
+	. = ALIGN(8);
 
 	.dynsym : {
 		__dyn_sym_start = .;
 		*(.dynsym)
 		__dyn_sym_end = .;
 	}
 
-	. = ALIGN(4);
+	. = ALIGN(8);
 
 	_end = .;
 

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)