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powerpc/t1023rdb: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <[email protected]> [York Sun: fix defconfig files] Reviewed-by: York Sun <[email protected]>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,6 +1,8 @@ | ||
| /* | ||
| * Copyright 2014 Freescale Semiconductor, Inc. | ||
| * | ||
| * Shengzhou Liu <[email protected]> | ||
| * | ||
| * SPDX-License-Identifier: GPL-2.0+ | ||
| */ | ||
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@@ -56,17 +58,25 @@ int board_eth_init(bd_t *bis) | |
| fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); | ||
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| switch (srds_s1) { | ||
| #ifdef CONFIG_T1024RDB | ||
| case 0x95: | ||
| /* set the on-board RGMII2 PHY */ | ||
| fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); | ||
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| /* set 10G XFI with Aquantia AQR105 PHY */ | ||
| fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); | ||
| break; | ||
| #endif | ||
| case 0x6a: | ||
| case 0x6b: | ||
| case 0x77: | ||
| case 0x135: | ||
| /* set the on-board 2.5G SGMII AQR105 PHY */ | ||
| fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR); | ||
| fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); | ||
| #ifdef CONFIG_T1023RDB | ||
| /* set the on-board 1G SGMII RTL8211F PHY */ | ||
| fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); | ||
| #endif | ||
| break; | ||
| default: | ||
| printf("SerDes protocol 0x%x is not supported on T102xRDB\n", | ||
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@@ -81,6 +91,14 @@ int board_eth_init(bd_t *bis) | |
| dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); | ||
| fm_info_set_mdio(i, dev); | ||
| break; | ||
| case PHY_INTERFACE_MODE_SGMII: | ||
| #if defined(CONFIG_T1023RDB) | ||
| dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); | ||
| #elif defined(CONFIG_T1024RDB) | ||
| dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); | ||
| #endif | ||
| fm_info_set_mdio(i, dev); | ||
| break; | ||
| case PHY_INTERFACE_MODE_SGMII_2500: | ||
| dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); | ||
| fm_info_set_mdio(i, dev); | ||
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@@ -110,13 +128,16 @@ int board_eth_init(bd_t *bis) | |
| void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, | ||
| enum fm_port port, int offset) | ||
| { | ||
| if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) && | ||
| (port == FM1_DTSEC3)) { | ||
| #if defined(CONFIG_T1024RDB) | ||
| if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) || | ||
| (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && | ||
| (port == FM1_DTSEC3)) { | ||
| fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); | ||
| fdt_setprop(fdt, offset, "phy-connection-type", | ||
| "sgmii-2500", 10); | ||
| fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); | ||
| } | ||
| #endif | ||
| } | ||
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| void fdt_fixup_board_enet(void *fdt) | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| #PBL preamble and RCW header for T1023RDB | ||
| aa55aa55 010e0100 | ||
| #SerDes Protocol: 0x77 | ||
| #Core/DDR: 1400Mhz/1600MT/s with single source clock | ||
| 0810000e 00000000 00000000 00000000 | ||
| 3b800003 00000012 e8104000 21000000 | ||
| 00000000 00000000 00000000 00020800 | ||
| 00000130 04020200 00000000 00000006 |
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