Merge branch 'master' of git://git.denx.de/u-boot-blackfin

cpu/blackfin/initcode.c

@@ -246,6 +246,15 @@ static inline void serial_putc(char c)
 #endif
 #endif
 
+/* Conflicting Column Address Widths Causes SDRAM Errors:
+ * EB2CAW and EB3CAW must be the same
+ */
+#if ANOMALY_05000362
+# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
+#  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
+# endif
+#endif
+
 BOOTROM_CALLED_FUNC_ATTR
 void initcode(ADI_BOOT_DATA *bootstruct)
 {
@@ -335,6 +344,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 	if (!ANOMALY_05000386) {
 		serial_putc('F');
 
+		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 		ADI_SYSCTRL_VALUES memory_settings;
 		uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
 		if (CONFIG_HAS_VR) {
@@ -355,6 +365,10 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 		bfrom_SysControl(actions, &memory_settings, NULL);
 #if ANOMALY_05000432
 		bfin_write_SIC_IWR1(-1);
+#endif
+#if ANOMALY_05000171
+		bfin_write_SICA_IWR0(-1);
+		bfin_write_SICA_IWR1(-1);
 #endif
 	} else {
 		serial_putc('G');
@@ -375,6 +389,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 
 		serial_putc('H');
 
+		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
 		bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
 
 		serial_putc('I');
@@ -397,7 +412,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
 		/* Only reprogram when needed to avoid triggering unnecessary
 		 * PLL relock sequences.
 		 */
-		if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+		if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
 			serial_putc('!');
 			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
 			asm("idle;");

cpu/blackfin/serial.c

@@ -24,6 +24,19 @@
  * Licensed under the GPL-2 or later.
  */
 
+/* Anomaly notes:
+ *  05000086 - we don't support autobaud
+ *  05000099 - we only use DR bit, so losing others is not a problem
+ *  05000100 - we don't use the UART_IIR register
+ *  05000215 - we poll the uart (no dma/interrupts)
+ *  05000225 - no workaround possible, but this shouldnt cause errors ...
+ *  05000230 - we tweak the baud rate calculation slightly
+ *  05000231 - we always use 1 stop bit
+ *  05000309 - we always enable the uart before we modify it in anyway
+ *  05000350 - we always enable the uart regardless of boot mode
+ *  05000363 - we don't support break signals, so don't generate one
+ */
+
 #include <common.h>
 #include <watchdog.h>
 #include <asm/blackfin.h>
@@ -43,7 +56,9 @@ uint16_t cached_rbr[256];
 size_t cache_count;
 
 /* The LSR is read-to-clear on some parts, so we have to make sure status
- * bits aren't inadvertently lost when doing various tests.
+ * bits aren't inadvertently lost when doing various tests.  This also
+ * works around anomaly 05000099 at the same time by keeping a cumulative
+ * tally of all the status bits.
  */
 static uint16_t uart_lsr_save;
 static uint16_t uart_lsr_read(void)
@@ -59,6 +74,10 @@ static void uart_lsr_clear(void)
 	*pUART_LSR |= -1;
 }
 #else
+/* When debugging is disabled, we only care about the DR bit, so if other
+ * bits get set/cleared, we don't really care since we don't read them
+ * anyways (and thus anomaly 05000099 is irrelevant).
+ */
 static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; }
 static inline void uart_lsr_clear(void) { *pUART_LSR = -1; }
 #endif

cpu/blackfin/serial.h

@@ -146,7 +146,7 @@ static inline void serial_early_init(void)
 	/* handle portmux crap on different Blackfins */
 	serial_do_portmux();
 
-	/* Enable UART */
+	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
 	*pUART_GCTL = UCEN;
 
 	/* Set LCR to Word Lengh 8-bit word select */

drivers/mtd/nand/bfin_nand.c

@@ -98,6 +98,7 @@ static void bfin_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 
 		/* Contents do not matter */
 		bfin_write_NFC_DATA_RD(0x0000);
+		SSYNC();
 
 		while (!(bfin_read_NFC_IRQSTAT() & RD_RDY))
 			if (ctrlc())

drivers/spi/bfin_spi.c

@@ -52,14 +52,28 @@ void spi_cs_activate(struct spi_slave *slave)
 		(read_SPI_FLG(bss) &
 		~((!bss->flg << 8) << slave->cs)) |
 		(1 << slave->cs));
+	SSYNC();
 	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
 __attribute__((weak))
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	write_SPI_FLG(bss, read_SPI_FLG(bss) & ~(1 << slave->cs));
+	u16 flg;
+
+	/* make sure we force the cs to deassert rather than let the
+	 * pin float back up.  otherwise, exact timings may not be
+	 * met some of the time leading to random behavior (ugh).
+	 */
+	flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+	write_SPI_FLG(bss, flg);
+	SSYNC();
+	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+	flg &= ~(1 << slave->cs);
+	write_SPI_FLG(bss, flg);
+	SSYNC();
 	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 

include/asm-blackfin/mach-bf527/anomaly.h

@@ -6,9 +6,9 @@
  * Licensed under the GPL-2 or later.
  */
 
-/* This file shoule be up to date with:
+/* This file should be up to date with:
  *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -25,14 +25,16 @@
 # define ANOMALY_BF527 0
 #endif
 
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
 #define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
 #define ANOMALY_05000245 (1)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (1)
 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
 #define ANOMALY_05000265 (1)
 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@@ -41,6 +43,8 @@
 #define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
 #define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
 #define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -75,8 +79,6 @@
 #define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* 8-Bit NAND Flash Boot Mode Not Functional */
 #define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
-/* Host Must Not Read Back During Host DMA Boot */
-#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Boot from OTP Memory Not Functional */
 #define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* bfrom_SysControl() Firmware Routine Not Functional */
@@ -129,7 +131,7 @@
 #define ANOMALY_05000416 (1)
 /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
 #define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
-/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
+/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
 #define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
 /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
 #define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
@@ -143,25 +145,46 @@
 #define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
 #define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 #define ANOMALY_05000426 (1)
 /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
 #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
 /* Software System Reset Corrupts PLL_LOCKCNT Register */
 #define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
+#define ANOMALY_05000431 (1)
 /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
 #define ANOMALY_05000432 (ANOMALY_BF526)
 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
 #define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+/* Preboot Cannot be Used to Alter the PLL_DIV Register */
+#define ANOMALY_05000439 (1)
+/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
+#define ANOMALY_05000440 (1)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
+/* The WURESET Bit in the SYSCR Register is not Functional */
+#define ANOMALY_05000445 (1)
+/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
+#define ANOMALY_05000451 (1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (1)
+/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
+#define ANOMALY_05000456 (1)
+/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
+#define ANOMALY_05000457 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000125 (0)
 #define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
 #define ANOMALY_05000183 (0)
 #define ANOMALY_05000198 (0)
+#define ANOMALY_05000227 (0)
 #define ANOMALY_05000230 (0)
+#define ANOMALY_05000242 (0)
 #define ANOMALY_05000244 (0)
 #define ANOMALY_05000261 (0)
 #define ANOMALY_05000263 (0)
@@ -174,6 +197,7 @@
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000312 (0)
 #define ANOMALY_05000323 (0)
+#define ANOMALY_05000362 (1)
 #define ANOMALY_05000363 (0)
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000447 (0)