Clean up usage of icache_disable/dcache_disable

There is no point in disabling the icache on 7xx/74xx/86xx parts and not also flushing the icache. All callers of invalidate_l1_instruction_cache() call icache_disable() right after. Make it so icache_disable() calls invalidate_l1_instruction_cache() for us. Also, dcache_disable() already calls dcache_flush() so there is no point in the explicit calls of dcache_flush(). Signed-off-by: Kumar Gala <[email protected]>
imaami · Aug 18, 2008 · fcd69a1 · fcd69a1
1 parent a15b071
commit fcd69a1
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Showing 8 changed files with 8 additions and 20 deletions.
diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c
@@ -51,9 +51,6 @@
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
@@ -930,7 +927,5 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c
@@ -51,9 +51,6 @@
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
@@ -930,7 +927,5 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
@@ -120,8 +120,6 @@ static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
 				     {"DRAMPLL_NDiv_1"},  /* 01 */
 				     {"DRAMPLL_NDiv_0"}}; /* 00 */
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
 extern flash_info_t flash_info[];
 
 /* ------------------------------------------------------------------------- */
@@ -961,8 +959,6 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
 

diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -37,8 +37,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
 extern void tsi108_init_f (void);
 
 int display_mem_map (void);

diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
@@ -62,8 +62,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
 extern flash_info_t flash_info[];
 
 /* ------------------------------------------------------------------------- */

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
@@ -236,8 +236,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * bios emulation, so turn them off again
 	 */
 	icache_disable();
-	invalidate_l1_instruction_cache();
-	flush_data_cache();
 	dcache_disable();
 #endif
 

diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S
@@ -245,6 +245,10 @@ _GLOBAL(icache_enable)
  * Disable L1 Instruction cache
  */
 _GLOBAL(icache_disable)
+	mflr	r4
+	bl	invalidate_l1_instruction_cache		/* uses r3 */
+	sync
+	mtlr	r4
 	mfspr	r3, HID0
 	li	r5, 0
 	ori	r5, r5, HID0_ICE

diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S
@@ -232,6 +232,10 @@ _GLOBAL(icache_enable)
  * Disable L1 Instruction cache
  */
 _GLOBAL(icache_disable)
+	mflr	r4
+	bl	invalidate_l1_instruction_cache		/* uses r3 */
+	sync
+	mtlr	r4
 	mfspr	r3, HID0
 	li	r5, 0
 	ori	r5, r5, HID0_ICE