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Merge tag 'clk-samsung-4.5' of git://linuxtv.org/snawrocki/samsung in…
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…to clk-next

drivers/clk/samsung updates (mostly bug fixes):
 - instantiation of the cpu clocks and addition of the GSCL
   IP parent clocks to the list of available consumer clocks
   for exynos542x SoCs;
 - MFC IP parent clock fix for exynos542x;
 - fix of locking bug in samsung/clk-cpu.c which caused
   system crashes with cpufreq enabled;
 - minor cleanup for s3c2410.
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@mturquette
mturquette committed Dec 22, 2015
2 parents b8f15e7 + c5e949c commit 1807b34
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Showing 4 changed files with 102 additions and 13 deletions.
10 changes: 6 additions & 4 deletions drivers/clk/samsung/clk-cpu.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -148,6 +148,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
unsigned long alt_prate = clk_get_rate(cpuclk->alt_parent);
unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;

/* find out the divider values to use for clock data */
while ((cfg_data->prate * 1000) != ndata->new_rate) {
Expand All @@ -156,7 +157,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
cfg_data++;
}

spin_lock(cpuclk->lock);
spin_lock_irqsave(cpuclk->lock, flags);

/*
* For the selected PLL clock frequency, get the pre-defined divider
Expand Down Expand Up @@ -212,7 +213,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
DIV_MASK_ALL);
}

spin_unlock(cpuclk->lock);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}

Expand All @@ -223,6 +224,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;

/* find out the divider values to use for clock data */
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
Expand All @@ -233,7 +235,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
}
}

spin_lock(cpuclk->lock);
spin_lock_irqsave(cpuclk->lock, flags);

/* select mout_apll as the alternate parent */
mux_reg = readl(base + E4210_SRC_CPU);
Expand All @@ -246,7 +248,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
}

exynos_set_safe_div(base, div, div_mask);
spin_unlock(cpuclk->lock);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}

Expand Down
98 changes: 91 additions & 7 deletions drivers/clk/samsung/clk-exynos5420.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
#include <linux/syscore_ops.h>

#include "clk.h"
#include "clk-cpu.h"

#define APLL_LOCK 0x0
#define APLL_CON0 0x100
Expand Down Expand Up @@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),

MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),

MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
Expand Down Expand Up @@ -677,8 +680,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
SRC_TOP5, 20, 1),
MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
SRC_TOP5, 28, 1),
MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),

MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
Expand Down Expand Up @@ -729,8 +732,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
SRC_TOP12, 20, 1),
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
SRC_TOP12, 28, 1),
MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),

/* DISP1 Block */
MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
Expand Down Expand Up @@ -926,7 +929,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
GATE_BUS_TOP, 13, 0, 0),
GATE(0, "aclk166", "mout_user_aclk166",
GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk333", "mout_aclk333",
GATE(0, "aclk333", "mout_user_aclk333",
GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
GATE_BUS_TOP, 16, 0, 0),
Expand Down Expand Up @@ -1246,6 +1249,74 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
KPLL_CON0, NULL),
};

#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((cpud) << 4)))

static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
{ 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
{ 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
{ 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
{ 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
{ 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
{ 0 },
};

static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
{ 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
{ 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
{ 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
{ 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
{ 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
{ 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
{ 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
{ 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
{ 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
{ 0 },
};

#define E5420_KFC_DIV(kpll, pclk, aclk) \
((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))

static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
{ 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 1300000, E5420_KFC_DIV(3, 5, 2), },
{ 1200000, E5420_KFC_DIV(3, 5, 2), },
{ 1100000, E5420_KFC_DIV(3, 5, 2), },
{ 1000000, E5420_KFC_DIV(3, 5, 2), },
{ 900000, E5420_KFC_DIV(3, 5, 2), },
{ 800000, E5420_KFC_DIV(3, 5, 2), },
{ 700000, E5420_KFC_DIV(3, 4, 2), },
{ 600000, E5420_KFC_DIV(3, 4, 2), },
{ 500000, E5420_KFC_DIV(3, 4, 2), },
{ 400000, E5420_KFC_DIV(3, 3, 2), },
{ 300000, E5420_KFC_DIV(3, 3, 2), },
{ 200000, E5420_KFC_DIV(3, 3, 2), },
{ 0 },
};

static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
Expand Down Expand Up @@ -1310,6 +1381,19 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}

if (soc == EXYNOS5420) {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
} else {
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
}
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);

exynos5420_clk_sleep_init();

samsung_clk_of_add_provider(np, ctx);
Expand Down
3 changes: 1 addition & 2 deletions drivers/clk/samsung/clk-s3c2410-dclk.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -77,12 +77,11 @@ static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
{
struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
int ret = 0;

s3c2410_modify_misccr((clkout->mask << clkout->shift),
(index << clkout->shift));

return ret;
return 0;
}

static const struct clk_ops s3c24xx_clkout_ops = {
Expand Down
4 changes: 4 additions & 0 deletions include/dt-bindings/clock/exynos5420.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,8 @@
#define CLK_FOUT_MPLL 10
#define CLK_FOUT_BPLL 11
#define CLK_FOUT_KPLL 12
#define CLK_ARM_CLK 13
#define CLK_KFC_CLK 14

/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
Expand Down Expand Up @@ -210,6 +212,8 @@
#define CLK_MOUT_SW_ACLK300 649
#define CLK_MOUT_USER_ACLK400_DISP1 650
#define CLK_MOUT_SW_ACLK400 651
#define CLK_MOUT_USER_ACLK300_GSCL 652
#define CLK_MOUT_SW_ACLK300_GSCL 653

/* divider clocks */
#define CLK_DOUT_PIXEL 768
Expand Down

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