clk: rockchip: rk3368: fix hdmi_cec gate-register

Fix a typo making the sclk_hdmi_cec access a wrong register to handle its gate. Fixes: 3536c97 ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <[email protected]> Reviewed-by: zhangqing <[email protected]> Cc: [email protected]
imesh · Jan 24, 2016 · fd0c074 · fd0c074
1 parent 0f28d98
commit fd0c074
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 			RK3368_CLKGATE_CON(4), 13, GFLAGS),
 	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
-			RK3368_CLKGATE_CON(5), 12, GFLAGS),
+			RK3368_CLKGATE_CON(4), 12, GFLAGS),
 
 	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 			RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,