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Merge git://git.denx.de/u-boot-fsl-qoriq
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@trini
trini committed Jun 28, 2016
2 parents 6f0aea3 + dee01e4 commit 44faff2
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Showing 12 changed files with 94 additions and 151 deletions.
8 changes: 5 additions & 3 deletions arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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Expand Up @@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include <fsl_ifc.h>
#include "cpu.h"

DECLARE_GLOBAL_DATA_PTR;

Expand Down Expand Up @@ -47,7 +48,7 @@ void get_sys_info(struct sys_info *sys_info)
[5] = 2, /* CC2 PPL / 2 */
};

uint i;
uint i, cluster;
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Expand Down Expand Up @@ -80,8 +81,9 @@ void get_sys_info(struct sys_info *sys_info)
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}

for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
cluster = fsl_qoriq_core_to_cluster(cpu);
u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
& 0xf;
u32 cplx_pll = core_cplx_pll[c_pll_sel];

Expand Down
4 changes: 2 additions & 2 deletions arch/arm/cpu/armv8/fsl-layerscape/soc.c
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Expand Up @@ -28,7 +28,7 @@ bool soc_has_dp_ddr(void)
u32 svr = gur_in32(&gur->svr);

/* LS2085A has DP_DDR */
if (SVR_SOC_VER(svr) == SVR_LS2085)
if (SVR_SOC_VER(svr) == SVR_LS2085A)
return true;

return false;
Expand All @@ -40,7 +40,7 @@ bool soc_has_aiop(void)
u32 svr = gur_in32(&gur->svr);

/* LS2085A has AIOP */
if (SVR_SOC_VER(svr) == SVR_LS2085)
if (SVR_SOC_VER(svr) == SVR_LS2085A)
return true;

return false;
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12 changes: 0 additions & 12 deletions arch/arm/dts/fsl-ls1012a.dtsi
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Expand Up @@ -9,18 +9,6 @@
/ {
compatible = "fsl,ls1012a";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;

cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&clockgen 1 0>;
};

};

sysclk: sysclk {
compatible = "fixed-clock";
Expand Down
32 changes: 0 additions & 32 deletions arch/arm/dts/fsl-ls1043a.dtsi
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Expand Up @@ -15,38 +15,6 @@
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;

cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&clockgen 1 0>;
};

cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&clockgen 1 0>;
};

cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
clocks = <&clockgen 1 0>;
};

cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
clocks = <&clockgen 1 0>;
};
};

sysclk: sysclk {
compatible = "fixed-clock";
Expand Down
61 changes: 0 additions & 61 deletions arch/arm/dts/fsl-ls2080a.dtsi
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Expand Up @@ -12,67 +12,6 @@
#address-cells = <2>;
#size-cells = <2>;

cpus {
#address-cells = <2>;
#size-cells = <0>;

/*
* We expect the enable-method for cpu's to be "psci", but this
* is dependent on the SoC FW, which will fill this in.
*
* Currently supported enable-method is psci v0.2
*/

/* We have 4 clusters having 2 Cortex-A57 cores each */
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
};

cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
};

cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
};

cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
};

cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
};

cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
};

cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
};

cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
};
};

memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
Expand Down
14 changes: 7 additions & 7 deletions arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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Expand Up @@ -8,13 +8,13 @@
#define _FSL_LAYERSCAPE_CPU_H

static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
CPU_TYPE_ENTRY(LS1023, LS1023, 2),
CPU_TYPE_ENTRY(LS2040, LS2040, 4),
CPU_TYPE_ENTRY(LS1012, LS1012, 1),
CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
};

#ifndef CONFIG_SYS_DCACHE_OFF
Expand Down
14 changes: 7 additions & 7 deletions arch/arm/include/asm/arch-fsl-layerscape/soc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -41,13 +41,13 @@ struct cpu_type {
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}

#define SVR_WO_E 0xFFFFFE
#define SVR_LS1012 0x870400
#define SVR_LS1043 0x879200
#define SVR_LS1023 0x879208
#define SVR_LS2045 0x870120
#define SVR_LS2080 0x870110
#define SVR_LS2085 0x870100
#define SVR_LS2040 0x870130
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
#define SVR_LS2040A 0x870130

#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
Expand Down
12 changes: 7 additions & 5 deletions board/freescale/ls1043aqds/ls1043aqds.c
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Original file line number Diff line number Diff line change
Expand Up @@ -47,16 +47,14 @@ enum {
int checkboard(void)
{
char buf[64];
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
#ifndef CONFIG_SD_BOOT
u8 sw;
#endif

puts("Board: LS1043AQDS, boot from ");

#ifdef CONFIG_SD_BOOT
puts("SD\n");
#elif defined(CONFIG_QSPI_BOOT)
puts("QSPI\n");
#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
Expand All @@ -67,8 +65,8 @@ int checkboard(void)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
else if (sw == 0x15)
printf("IFCCard\n");
else if (sw == 0xF)
printf("QSPI\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
Expand Down Expand Up @@ -232,6 +230,10 @@ int board_early_init_f(void)
#ifdef CONFIG_LPUART
u8 uart;
#endif

#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
fsl_lsch2_early_init_f();

#ifdef CONFIG_HAS_FSL_XHCI_USB
Expand Down
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