MICROZED: GRIZZLY: add custom CONFIG_EXTRA_ENV_SETTINGS

arch/arm/dts/Makefile

@@ -97,7 +97,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm011.dtb \
 	zynq-zc770-xm012.dtb \
-	zynq-zc770-xm013.dtb
+	zynq-zc770-xm013.dtb \
+	zynq-grizzly.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-ep108.dtb			\
 	zynqmp-zcu100.dtb			\

arch/arm/dts/zynq-grizzly.dts

@@ -0,0 +1,70 @@
+/*
+ * Grizzly board DTS
+ *
+ * Copyright (C) 2013 - 2016 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Grizzly Board";
+	compatible = "xlnx,zynq-grizzly", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+		spi0 = &qspi;
+		mmc0 = &sdhci0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x20000000>;
+	};
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&uart1 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&sdhci0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};

configs/zynq_grizzly_defconfig

@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-grizzly"
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_NO_FLASH=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="grizzly> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
+# CONFIG_SPI_FLASH_STMICRO is not set
+# CONFIG_SPI_FLASH_WINBOND is not set
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300

include/configs/zynq_grizzly.h

@@ -0,0 +1,50 @@
+/*
+ * Configuration settings for the ImSAR Grizzly board
+ * See zynq_common.h for Zynq common configs
+ */
+
+#ifndef __CONFIG_ZYNQ_GRIZZLY_H
+#define __CONFIG_ZYNQ_GRIZZLY_H
+
+#define CONFIG_ZYNQ_PS_CLK_FREQ  50000000UL
+
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_EEPROM
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bitsz=0x0109C0F6\0" \
+	"bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait earlyprintk\0" \
+	"clear=sf probe 0 && sf erase 80000 20000\0" \
+	"devicetree_image=devicetree.dtb\0" \
+	"ethaddr=00:0a:35:00:01:22\0" \
+	"fdt_high=0x20000000\0"	\
+	"fpga_buff=0x0100000\0" \
+	"fpga_offset=0x100000\0" \
+	"grizzlyboot=qspiboot sdboot\0" \
+	"kernel_image=uImage\0" \
+	"read_fpga=echo Loading FPGA from QSPI && sf probe 0 0 0 && sf read ${fpga_buff} ${fpga_offset} ${bitsz}\0" \
+	"load_bit=echo Loading bit file && fpga loadb 0 ${fpga_buff} ${bitsz}\0" \
+	"qspiboot=run read_fpga && run load_bit || " \
+		"echo FPGA load failed && setenv devicetree_image fallback.dtb\0" \
+	"sdboot=echo Copying Linux from SD to RAM... && " \
+		"mmcinfo && " \
+		"fatload mmc 0 0x3000000 ${kernel_image} && " \
+		"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
+		"bootm 0x3000000 - 0x2A00000\0"
+
+#include <configs/zynq-common.h>
+
+#undef  CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND		"run $grizzlyboot"
+
+#endif /* __CONFIG_ZYNQ_GRIZZLY_H */

include/configs/zynq_microzed.h

@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_MICROZED_H
+#define __CONFIG_ZYNQ_MICROZED_H
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs=console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait \0" \
+	"ethaddr=00:0a:35:00:01:22\0" \
+	"fdt_high=0x20000000\0"	\
+	"devicetree_image=devicetree.dtb\0" \
+	"kernel_image=uImage\0" \
+	"kernel_size=0x500000\0"	\
+	"devicetree_size=0x20000\0"	\
+	"ramdisk_size=0x5E0000\0"	\
+	"qspiboot=echo Copying Linux from QSPI flash to RAM... && " \
+		"sf probe 0 0 0 && " \
+		"sf read 0x3000000 0x100000 ${kernel_size} && " \
+		"sf read 0x2A00000 0x600000 ${devicetree_size} && " \
+		"echo Copying ramdisk... && " \
+		"sf read 0x2000000 0x620000 ${ramdisk_size} && " \
+		"bootm 0x3000000 0x2000000 0x2A00000\0" \
+	"sdboot=echo Copying Linux from SD to RAM... && " \
+		"mmcinfo && " \
+		"fatload mmc 0 0x3000000 ${kernel_image} && " \
+		"fatload mmc 0 0x2A00000 ${devicetree_image} && " \
+		"bootm 0x3000000 - 0x2A00000\0" \
+	"bitstream_image=fpga.bit\0" \
+	"bootcmd=run mmc_loadbit_fat; run sdboot\0" \
+	"loadbit_addr=0x100000\0" \
+	"mmc_loadbit_fat=echo \"Loading bitstream from SD/MMC/eMMC to RAM..\" && " \
+		"mmcinfo && fatload mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga loadb 0 ${loadbit_addr} ${filesize}\0"
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_MICROZED_H */