QAT engine AES-CCM support

-Added Fix for s_server issue in aes-ccm -offloaded 192 & 256 to openssl when no 2.0 driver -Added small packet offload support to AES-CCM -Added Testapp support for AES-CCM -Added SVM support for AES-CCM -Addressed AES-CCM Review Comments Signed-off-by: Premkumar Shanmugam <[email protected]>
intel · Dec 27, 2023 · 6b617ee · 6b617ee
1 parent b83bdc3
commit 6b617ee
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Showing 25 changed files with 4,680 additions and 801 deletions.
diff --git a/Makefile.am b/Makefile.am
@@ -94,7 +94,8 @@ if QAT_HW
               qat_hw_chachapoly.c  \
               qat_hw_sm4_cbc.c     \
               qat_hw_sm3.c         \
-              qat_hw_sm2.c
+              qat_hw_sm2.c         \
+              qat_hw_ccm.c
 endif
 
 if QAT_SW

diff --git a/configure.ac b/configure.ac
@@ -94,6 +94,11 @@ AC_ARG_ENABLE(qat_hw_sm3,
                              [Enable qat_hw SM3 acceleration]))
 AC_SUBST(enable_qat_hw_sm3)
 
+AC_ARG_ENABLE(qat_hw_ccm,
+              AS_HELP_STRING([--disable-qat_hw_ccm],
+                             [Disable qat_hw AES-CCM acceleration]))
+AC_SUBST(enable_qat_hw_ccm)
+
 AC_ARG_ENABLE(qat_sw_gcm,
               AS_HELP_STRING([--disable-qat_sw_gcm],
                              [Disable qat_sw AES-GCM acceleration]))
@@ -502,6 +507,7 @@ then
     AC_SUBST([enable_qat_hw_ecx], ["no"])
     AC_SUBST([enable_qat_hw_gcm], ["no"])
     AC_SUBST([enable_qat_hw_sm2], ["no"])
+    AC_SUBST([enable_qat_hw_ccm], ["no"])
   fi
   if test "x$cflags_qat_sw" != "x"
   then
@@ -564,6 +570,8 @@ then
         [cflags_qat_hw="${cflags_qat_hw} -DENABLE_QAT_HW_SM4_CBC"; AC_MSG_NOTICE([Accelerating SM4-CBC to Hardware])])
   AS_IF([test "x$enable_qat_hw_sm2" = "xyes"],
         [cflags_qat_hw="${cflags_qat_hw} -DENABLE_QAT_HW_SM2"; AC_MSG_NOTICE([Accelerating SM2 to Hardware])])
+  AS_IF([test "x$enable_qat_hw_ccm" != "xno"],
+        [cflags_qat_hw="${cflags_qat_hw} -DENABLE_QAT_HW_CCM"; AC_MSG_NOTICE([Accelerating AES-CCM to Hardware])])
 fi
 
 # Enable QAT_SW Algorithms based on enable/disable Flags

diff --git a/docs/config_options.md b/docs/config_options.md
@@ -154,6 +154,9 @@ The following is a list of the options that can be used with the
 --disable-qat_hw_gcm/--enable-qat_hw_gcm
     Disable/Enable Intel(R) QAT Hardware AES-GCM acceleration (disabled by default).
 
+--disable-qat_hw_ccm/--enable-qat_hw_ccm
+    Disable/Enable Intel(R) QAT Hardware AES-CCM acceleration (enabled by default).
+
 --disable-qat_hw_sm4_cbc/--enable-qat_hw_sm4_cbc
     Disable/Enable Intel(R) QAT Hardware SM4-CBC acceleration.(disabled by default)
     This flag is valid only on 4xxx(QAT gen 4 devices) as the support is not available

diff --git a/docs/features.md b/docs/features.md
@@ -18,7 +18,7 @@
 * Symmetric Chained Cipher acceleration with pipelining capability:
     * AES128-CBC-HMAC-SHA1/AES256-CBC-HMAC-SHA1.
     * AES128-CBC-HMAC-SHA256/AES256-CBC-HMAC-SHA256.
-* Symmetric ciphers AES128-GCM and AES256-GCM
+* Symmetric ciphers AES128-CCM, AES128-GCM and AES256-GCM
 * Pseudo Random Function (PRF) Acceleration.
 * [HMAC Key Derivation Function (HKDF) Acceleration.](qat_hw.md#intel-qat-openssl-engine-hkdf-support)
 * [Pipelined Operations](qat_hw.md#using-the-openssl-pipelining-capability)
@@ -32,6 +32,7 @@
   *  ChaCha20-Poly1305
   *  SM2 (Not supported in qatlib)
   *  SM3 (Not supported in qatlib)
+  *  AES128-CCM, AES192-CCM and AES256-CCM
 
 Please refer [here](qat_hw_algo.md) for supported platforms list and default behaviour.
 

diff --git a/docs/qat_coex.md b/docs/qat_coex.md
@@ -54,6 +54,7 @@ and the bit map of each algorithm is defined below:
 | SM3 | 0x08000 | SW |
 | SM4-GCM | 0x10000 | SW |
 | SM4-CCM | 0x20000 | SW |
+| AES-CCM | 0x40000 | HW |
 
 ## QAT_HW & QAT_SW Co-existence recommended settings and working mechanism
 

diff --git a/docs/qat_hw_algo.md b/docs/qat_hw_algo.md
@@ -17,6 +17,9 @@
 | PRF | * | * | * | * |
 | AES-128-GCM | *** | *** | *** | *** |
 | AES-256-GCM | *** | *** | *** | *** |
+| AES-128-CCM | * | * | * | * |
+| AES-192-CCM |  |  | * | * |
+| AES-256-CCM |  |  | * | * |
 | AES128_CBC_HMAC_SHA1 | ** | ** | ** | ** |
 | AES256_CBC_HMAC_SHA1 | ** | ** | ** | ** |
 | AES128_CBC_HMAC_SHA256 | * | * | * | * |

diff --git a/e_qat.c b/e_qat.c
@@ -93,6 +93,7 @@
 # include "qat_hw_dsa.h"
 # include "qat_hw_dh.h"
 # include "qat_hw_gcm.h"
+# include "qat_hw_ccm.h"
 #endif /* QAT_BORINGSSL */
 
 /* QAT includes */
@@ -214,6 +215,7 @@ int qat_sw_sm3_offload = 0;
 int qat_sw_sm4_cbc_offload = 0;
 int qat_sw_sm4_gcm_offload = 0;
 int qat_sw_sm4_ccm_offload = 0;
+int qat_hw_aes_ccm_offload = 0;
 int qat_hw_keep_polling = 1;
 int qat_sw_keep_polling = 1;
 int enable_external_polling = 0;

diff --git a/e_qat.h b/e_qat.h
@@ -428,6 +428,7 @@ extern int qat_sw_sm3_offload;
 extern int qat_sw_sm4_cbc_offload;
 extern int qat_sw_sm4_gcm_offload;
 extern int qat_sw_sm4_ccm_offload;
+extern int qat_hw_aes_ccm_offload;
 extern int qat_hw_keep_polling;
 extern int qat_sw_keep_polling;
 extern int enable_external_polling;
@@ -473,6 +474,7 @@ extern int qat_fips_service_indicator;
 #define ALGO_ENABLE_MASK_SM3                0x08000
 #define ALGO_ENABLE_MASK_SM4_GCM            0x10000
 #define ALGO_ENABLE_MASK_SM4_CCM            0x20000
+#define ALGO_ENABLE_MASK_AES_CCM            0x40000
 
 extern int qat_reload_algo;
 extern uint64_t qat_hw_algo_enable_mask;