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Commits on May 4, 2018

• [LICM] Compute a must execute property for the prefix of the header as we go

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  preames

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• AMDGPU/NFC: Fix formatting for 900, 902 ISA Version features

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  kzhuravl

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• AMDGPU: Add D16 instructions preserve unused bits feature

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  kzhuravl

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• [MachineLICM] Debug intrinsics shouldn't affect hoist decisions

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  geoffberry

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• [ObjCARC] Account for catchswitch in bitcast insertion

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  smeenai

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• Fast Math Flag mapping into SDNode

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  Michael Berg

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• [X86] Add WriteEMMS scheduler class

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  RKSimon

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• [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.

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  RKSimon

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• [LoopIdiomRecognize] Don't create an IRBuilder just to call getTrue/getFalse.

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  topperc

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• DwarfCompileUnit: Fix another assertion failure on malformed input

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  adrian-prantl

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• [llvm-exegesis] Fix pfm counter names for BDW.

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  legrosbuffle

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• [X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.

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  RKSimon

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• [Hexagon] Remove leftover debugging code after r331527

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  Krzysztof Parzyszek

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• [Hexagon] Handle non-immediate constants in HexagonSplitDouble

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  Krzysztof Parzyszek

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• [mips] Correct the predicates of sign extension instructions

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  Simon Dardis

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• [X86] Add WriteVecMOVMSKY scheduler class

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  RKSimon

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• [AArch64] Custom Lower MULLH{S,U} for v16i8, v8i16, and v4i32

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  zatrazz

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• [Hexagon] Skip reserved physical registers when updating liveness

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  Krzysztof Parzyszek

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• [X86] Add SchedWriteFRnd fp rounding scheduler classes

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  RKSimon

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• [SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI

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  bjope

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• [RegUsageInfoCollector] Bugfix for handling of register aliases.

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  JonPsson

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• [IRCE] Fix misuse of dyn_cast which leads to UB

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  Max Kazantsev

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• [MachineCSE] Rewrite a loop checking if a block is in a set of blocks without using a set. NFC.

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  Michael Zolotukhin

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• [LoopIdiomRecognize] Replace more unchecked dyn_casts with cast.

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  topperc

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• [LoopIdiomRecognize] Use a regular array instead of a SmallVector and explicit ArrayRef.

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• [LoopIdiomRecognize] Turn two uncheck dyn_casts into regular casts.

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Commits on May 3, 2018

• AMDGPU: Make getSubRegFromChannel a static member of AMDGPURegisterInfo

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  tstellar

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• [X86] Add WriteDPPD/WriteDPPS dot product scheduler classes

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  RKSimon

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• [X86][Znver1] Use SchedAlias to tag microcoded scheduler classes

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  RKSimon

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• Fix include of config.h that was incorrectly changed in r331184

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  bogner

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• [InstCombine] refine select-of-constants to bitwise ops

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  rotateright

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• GlobalISel: Use a callback to compute constrained reg class for unallocatble registers

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  tstellar

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• [ThinLTO] Add support for optimization remarks to thinBackend

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  teresajohnson

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• [X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.

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  RKSimon

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• [X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes

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  RKSimon

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