Confluence Markup Builder Plugin for Sphinx

Embedded C/C++ web server

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

A place to share libraries and utilities that don't belong in the core bsc repo

Bluespec Compiler (BSC)

Sail RISC-V model

Backend-agnostic network configuration in YAML

This is mainly a simulation library of xilinx primitives that are verilator compatible.

Mirror of official clang git repository located at http://llvm.org/git/clang. Updated every five minutes.

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Riscy Processors - Open-Sourced RISC-V Processors

Whitelist of apt packages approved for build environments with restricted sudo

Example design for FPGA Drive using the AXI Memory Mapped to PCI Express Bridge IP

Django Cassandra Engine - the Cassandra backend for Django

GNU toolchain for RISC-V, including GCC 5.3.0

Whitelist of apt sources approved for build environments with restricted sudo

llvm runtime interpreter/translator

Python-based continuous integration testing framework; your pull requests are more than welcome!

QEMU with RISC-V Emulation Support

The official Linux kernel from Xilinx

RISC-V Linux Port

Spike, a RISC-V ISA Simulator