core: avoid incremental linking with -gc

The AArch64 linkers seems to have occasional problems with incremental
linking (-i) in combination with garbage collect of sections (-gc). The
way we're organizing the layout of the binary used for paging depends on
-gc to build the different dependency trees for unpaged and
initialization code.

The problem in the linker is tracked in
https://bugs.linaro.org/show_bug.cgi?id=3006 and
https://sourceware.org/bugzilla/show_bug.cgi?id=21524

The problem typically manifests itself by:
aarch64-toolchain/gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-ld: BFD (Linaro_Binutils-2017.02) 2.27.0.20161019 assertion fail /home/tcwg-buildslave/workspace/tcwg-make-release/label/docker-trusty-amd64-tcwg-build/target/aarch64-linux-gnu/snapshots/binutils-gdb.git~linaro_binutils-2_27-branch/bfd/elflink.c:8380
core/arch/arm/kernel/link.mk:90: recipe for target 'out/arm-plat-vexpress/core/init.o' failed
make: *** [out/arm-plat-vexpress/core/init.o] Error 1

With this patch we replace the incremental linking with a full link
using a special link script. With a full link we can't have undefined
symbols so some dummy symbols are provided by the link script when some
object files are skipped when reducing the dependency tree. To
completely get rid of those dummy symbols the script that gathers the
sections is replaced by a python script that skips listed sections (if
provided).

In terms of features in the resulting binary, nothing is changed in this
commit.

Reviewed-by: Volodymyr Babchuk <[email protected]>
Acked-by: Jerome Forissier <[email protected]>
Signed-off-by: Jens Wiklander <[email protected]>

core/arch/arm/kernel/link.mk

@@ -1,5 +1,6 @@
 link-out-dir = $(out-dir)/core
 
+link-script-dummy = core/arch/arm/kernel/link_dummy.ld
 link-script = $(platform-dir)/kern.ld.S
 link-script-pp = $(link-out-dir)/kern.ld
 link-script-dep = $(link-out-dir)/.kern.ld.d
@@ -31,7 +32,8 @@ entries-unpaged += core_init_mmu_regs
 entries-unpaged += sem_cpu_sync
 entries-unpaged += generic_boot_get_handlers
 
-ldargs-all_objs := -i $(objs) $(link-ldadd) $(libgcccore)
+ldargs-all_objs := -T $(link-script-dummy) --no-check-sections \
+	$(objs) $(link-ldadd) $(libgcccore)
 cleanfiles += $(link-out-dir)/all_objs.o
 $(link-out-dir)/all_objs.o: $(objs) $(libdeps) $(MAKEFILE_LIST)
 	@$(cmd-echo-silent) '  LD      $@'
@@ -43,11 +45,13 @@ $(link-out-dir)/unpaged_entries.txt: $(link-out-dir)/all_objs.o
 	$(q)$(NMcore) $< | \
 		$(AWK) '/ ____keep_pager/ { printf "-u%s ", $$3 }' > $@
 
+funcs-unpaged-rem += .text.tee_entry_std .text.tee_svc_handler
 objs-unpaged-rem += core/arch/arm/tee/entry_std.o
 objs-unpaged-rem += core/arch/arm/tee/arch_svc.o
 objs-unpaged := \
 	$(filter-out $(addprefix $(out-dir)/, $(objs-unpaged-rem)), $(objs))
-ldargs-unpaged = -i --gc-sections $(addprefix -u, $(entries-unpaged))
+ldargs-unpaged = -T $(link-script-dummy) --no-check-sections --gc-sections \
+		$(addprefix -u, $(entries-unpaged))
 ldargs-unpaged-objs := $(objs-unpaged) $(link-ldadd) $(libgcccore)
 cleanfiles += $(link-out-dir)/unpaged.o
 $(link-out-dir)/unpaged.o: $(link-out-dir)/unpaged_entries.txt
@@ -59,13 +63,14 @@ $(link-out-dir)/unpaged.o: $(link-out-dir)/unpaged_entries.txt
 cleanfiles += $(link-out-dir)/text_unpaged.ld.S
 $(link-out-dir)/text_unpaged.ld.S: $(link-out-dir)/unpaged.o
 	@$(cmd-echo-silent) '  GEN     $@'
-	$(q)$(READELFcore) -a -W $< | ${AWK} -f ./scripts/gen_ld_text_sects.awk > $@
+	$(q)$(READELFcore) -S -W $< | \
+		./scripts/gen_ld_sects.py .text. $(funcs-unpaged-rem) > $@
 
 cleanfiles += $(link-out-dir)/rodata_unpaged.ld.S
 $(link-out-dir)/rodata_unpaged.ld.S: $(link-out-dir)/unpaged.o
 	@$(cmd-echo-silent) '  GEN     $@'
-	$(q)$(READELFcore) -a -W $< | \
-		${AWK} -f ./scripts/gen_ld_rodata_sects.awk > $@
+	$(q)$(READELFcore) -S -W $< | \
+		./scripts/gen_ld_sects.py .rodata. > $@
 
 
 cleanfiles += $(link-out-dir)/init_entries.txt
@@ -74,15 +79,16 @@ $(link-out-dir)/init_entries.txt: $(link-out-dir)/all_objs.o
 	$(q)$(NMcore) $< | \
 		$(AWK) '/ ____keep_init/ { printf "-u%s", $$3 }' > $@
 
-objs-init-rem += core/arch/arm/tee/arch_svc.o
-objs-init-rem += core/arch/arm/tee/arch_svc_asm.o
+funcs-init-rem = $(funcs-unpaged-rem)
+funcs-init-rem += .text.init_teecore
+objs-init-rem = $(objs-unpaged-rem)
 objs-init-rem += core/arch/arm/tee/init.o
-objs-init-rem += core/arch/arm/tee/entry_std.o
 entries-init += _start
 objs-init := \
 	$(filter-out $(addprefix $(out-dir)/, $(objs-init-rem)), $(objs) \
 		$(link-out-dir)/version.o)
-ldargs-init := -i --gc-sections $(addprefix -u, $(entries-init))
+ldargs-init := -T $(link-script-dummy) --no-check-sections --gc-sections \
+		$(addprefix -u, $(entries-init))
 
 ldargs-init-objs := $(objs-init) $(link-ldadd) $(libgcccore)
 cleanfiles += $(link-out-dir)/init.o
@@ -96,13 +102,13 @@ $(link-out-dir)/init.o: $(link-out-dir)/init_entries.txt
 cleanfiles += $(link-out-dir)/text_init.ld.S
 $(link-out-dir)/text_init.ld.S: $(link-out-dir)/init.o
 	@$(cmd-echo-silent) '  GEN     $@'
-	$(q)$(READELFcore) -a -W $< | ${AWK} -f ./scripts/gen_ld_text_sects.awk > $@
+	$(q)$(READELFcore) -S -W $< | \
+		./scripts/gen_ld_sects.py .text. $(funcs-init-rem) > $@
 
 cleanfiles += $(link-out-dir)/rodata_init.ld.S
 $(link-out-dir)/rodata_init.ld.S: $(link-out-dir)/init.o
 	@$(cmd-echo-silent) '  GEN     $@'
-	$(q)$(READELFcore) -a -W $< | \
-		${AWK} -f ./scripts/gen_ld_rodata_sects.awk > $@
+	$(q)$(READELFcore) -S -W $< | ./scripts/gen_ld_sects.py .rodata. > $@
 
 -include $(link-script-dep)
 

core/arch/arm/kernel/link_dummy.ld

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2017, Linaro Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+SECTIONS
+{
+	/*
+	 * This seems to make the ARMv7 linker happy with regards to glue_7
+	 * sections etc.
+	 */
+	..dummy : { }
+}
+
+__asan_shadow_end = .;
+__asan_shadow_start = .;
+__bss_end = .;
+__bss_start = .;
+__ctor_end = .;
+__ctor_list = .;
+__data_end = .;
+__early_bss_end = .;
+__early_bss_start = .;
+__end = .;
+__end_phys_mem_map_section = .;
+__end_phys_sdp_mem_section = .;
+__exidx_end = .;
+__exidx_start = .;
+__heap1_end = .;
+__heap1_start = .;
+__heap2_end = .;
+__heap2_start = .;
+__initcall_end = .;
+__initcall_start = .;
+__init_end = .;
+__init_size = .;
+__init_start = .;
+__nozi_end = .;
+__nozi_stack_end = .;
+__nozi_stack_start = .;
+__nozi_start = .;
+__pageable_end = .;
+__pageable_part_end = .;
+__pageable_part_start = .;
+__pageable_start = .;
+__rodata_dtdrv_end = .;
+__rodata_dtdrv_start = .;
+__rodata_end = .;
+__rodata_start = .;
+__text_init_start = .;
+__text_start = .;
+__tmp_hashes_end = .;
+__tmp_hashes_size = .;
+__tmp_hashes_start = .;
+__vcore_init_ro_size = .;
+__vcore_init_ro_start = .;
+__vcore_init_rx_size = .;
+__vcore_init_rx_start = .;
+__vcore_unpg_ro_size = .;
+__vcore_unpg_ro_start = .;
+__vcore_unpg_rw_size = .;
+__vcore_unpg_rw_start = .;
+__vcore_unpg_rx_size = .;
+__vcore_unpg_rx_start = .;
+PROVIDE(core_v_str = 0);
+PROVIDE(tee_entry_std = 0);
+PROVIDE(tee_svc_handler = 0);
+PROVIDE(init_teecore = 0);

core/arch/arm/plat-vexpress/sub.mk

@@ -4,4 +4,4 @@ ifeq ($(PLATFORM_FLAVOR_juno),y)
 srcs-$(CFG_ARM32_core) += juno_core_pos_a32.S
 srcs-$(CFG_ARM64_core) += juno_core_pos_a64.S
 endif
-srcs-y += vendor_props.c
+srcs-$(CFG_WITH_USER_TA) += vendor_props.c

core/tee/tee_svc_storage.c

@@ -151,6 +151,7 @@ TEE_Result tee_svc_storage_create_filename(void *buf, size_t blen,
 	return TEE_SUCCESS;
 }
 
+#ifdef CFG_REE_FS
 /* "/dirf.db" or "/<file number>" */
 TEE_Result
 tee_svc_storage_create_filename_dfh(void *buf, size_t blen,
@@ -171,6 +172,7 @@ tee_svc_storage_create_filename_dfh(void *buf, size_t blen,
 	l = blen - pos;
 	return tee_fs_dirfile_fileh_to_fname(dfh, file + pos, &l);
 }
+#endif
 
 /* "/TA_uuid" */
 TEE_Result tee_svc_storage_create_dirname(void *buf, size_t blen,

scripts/gen_ld_rodata_sects.awk → scripts/gen_ld_sects.py

@@ -1,5 +1,6 @@
+#!/usr/bin/env python
 #
-# Copyright (c) 2014, Linaro Limited
+# Copyright (c) 2017, Linaro Limited
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -25,31 +26,58 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-BEGIN {
-	in_shdr = 0;
-}
-
-/Section Headers:/ {
-	in_shdr = 1;
-	next;
-}
-
-/Key to Flags:/ {
-	in_shdr = 0;
-	next;
-}
-
-{
-	if (in_shdr) {
-		if ($1 == "[")
-			name_offs = 3;
-		else
-			name_offs = 2;
-
-		name = $(name_offs);
-		type = $(name_offs + 1);
-		flags = $(name_offs + 6);
-		if (name ~ /^\.rodata\./ && type == "PROGBITS")
-			printf "\t*(%s)\n", name;
-	}
-}
+import sys
+import re
+
+def usage():
+	print "Usage: {} <section reg exp match> [<skip section>...]".format( \
+		sys.argv[0])
+	sys.exit (1)
+
+def main():
+	if len(sys.argv) < 2 :
+		usage()
+
+	in_shdr = False
+	section_headers = re.compile("Section Headers:")
+	key_to_flags = re.compile("Key to Flags:")
+	match_rule = re.compile(sys.argv[1])
+	skip_sections = sys.argv[2:]
+
+	for line in sys.stdin:
+		if section_headers.match(line) :
+			in_shdr = True;
+			continue
+		if key_to_flags.match(line) :
+			in_shdr = False;
+			continue
+
+		if not in_shdr :
+			continue
+
+		words = line.split()
+
+		if len(words) < 3 :
+			continue
+
+		if words[0] == "[" :
+			name_offs = 2
+		else :
+			name_offs = 1;
+
+		sect_name = words[name_offs]
+		sect_type = words[name_offs + 1]
+
+		if sect_type != "PROGBITS" :
+			continue
+
+		if not match_rule.match(sect_name) :
+			continue
+
+		if sect_name in skip_sections :
+			continue
+
+		print '\t*({})'.format(sect_name)
+
+if __name__ == "__main__":
+        main()