ARM: dts: aspeed-g5: Sort LPC child nodes by unit address

Lets try to maintain some sort of sanity. Signed-off-by: Andrew Jeffery <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Joel Stanley <[email protected]>
jangid · Dec 17, 2019 · cf4aae1 · cf4aae1
1 parent e3f0cf4
commit cf4aae1
Showing 1 changed file with 6 additions and 5 deletions.
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -474,17 +474,18 @@
 						status = "disabled";
 					};
 
-					lhc: lhc@20 {
-						compatible = "aspeed,ast2500-lhc";
-						reg = <0x20 0x24 0x48 0x8>;
-					};
-
 					lpc_reset: reset-controller@18 {
 						compatible = "aspeed,ast2500-lpc-reset";
 						reg = <0x18 0x4>;
 						#reset-cells = <1>;
 					};
 
+					lhc: lhc@20 {
+						compatible = "aspeed,ast2500-lhc";
+						reg = <0x20 0x24 0x48 0x8>;
+					};
+
+
 					ibt: ibt@c0 {
 						compatible = "aspeed,ast2500-ibt-bmc";
 						reg = <0xc0 0x18>;