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axi_intf: Add aw_prot and ar_prot modports to AXI_LITE, AXI_LITE_DV, …
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…Update test infrastructure
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@andreaskurth
Wolfgang Rönninger authored and andreaskurth committed May 6, 2020
1 parent fc241de commit 0fbb47c
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Showing 7 changed files with 147 additions and 108 deletions.
15 changes: 15 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -10,6 +10,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
### Added

### Changed
- `axi_intf`: Add in `AXI_LITE` and `AXI_LITE_DV` the modports `aw_prot` and `ar_prot`.
- `include/axi/assign`: Adapt ASSIGN macros of AXI_LITE for modports `aw_prot` and `ar_prot`.
- `axi_test::axi_lite_driver`: Adapt for new modports `aw_prot` and `ar_prot`.
- `send_aw()`: Add input `axi_pkg::prot_t prot`.
- `send_ar()`: Add input `axi_pkg::prot_t prot`.
- `recv_aw()`: Add output `axi_pkg::prot_t prot`.
- `recv_ar()`: Add output `axi_pkg::prot_t prot`.
- `axi_test::rand_axi_lite_master`: Adapt for new modports `aw_prot` and `ar_prot`.
- `send_aws()`: Add random `aw_prot` on each AW.
- `send_ars()`: Add random `ar_prot` on each AR.
- `write()`: Add input `axi_pkg::prot_t w_prot`.
- `read()`: Add input `axi_pkg::prot_t r_prot`.
- `axi_test::rand_axi_lite_slave`: Adapt for new modports `aw_prot` and `ar_prot`, display prot.
- Update usage of `axi_test::*axi_lite*` in tbs: `tb_axi_lite_mailbox`, `tb_axi_lite_to_axi` and
`tb_axi_lite_xbar` to the changes in `axi_test`.

### Fixed

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14 changes: 8 additions & 6 deletions include/axi/assign.svh
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Expand Up @@ -401,6 +401,7 @@
// `AXI_LITE_ASSIGN_R(dst, src)
`define AXI_LITE_ASSIGN_AW(dst, src) \
assign dst.aw_addr = src.aw_addr; \
assign dst.aw_prot = src.aw_prot; \
assign dst.aw_valid = src.aw_valid; \
assign src.aw_ready = dst.aw_ready;
`define AXI_LITE_ASSIGN_W(dst, src) \
Expand All @@ -414,6 +415,7 @@
assign src.b_ready = dst.b_ready;
`define AXI_LITE_ASSIGN_AR(dst, src) \
assign dst.ar_addr = src.ar_addr; \
assign dst.ar_prot = src.ar_prot; \
assign dst.ar_valid = src.ar_valid; \
assign src.ar_ready = dst.ar_ready;
`define AXI_LITE_ASSIGN_R(dst, src) \
Expand All @@ -435,16 +437,16 @@
// assignments (with `opt_as = assign`) and assignments inside processes (with `opt_as` void) with
// the same code.
`define AXI_LITE_FROM_AW(opt_as, axi_lite_if, aw_lite_struct) \
opt_as axi_lite_if.aw_addr = aw_lite_struct.addr;
// prot not in interface!
opt_as axi_lite_if.aw_addr = aw_lite_struct.addr; \
opt_as axi_lite_if.aw_prot = aw_lite_struct.prot;
`define AXI_LITE_FROM_W(opt_as, axi_lite_if, w_lite_struct) \
opt_as axi_lite_if.w_data = w_lite_struct.data; \
opt_as axi_lite_if.w_strb = w_lite_struct.strb;
`define AXI_LITE_FROM_B(opt_as, axi_lite_if, b_lite_struct) \
opt_as axi_lite_if.b_resp = b_lite_struct.resp;
`define AXI_LITE_FROM_AR(opt_as, axi_lite_if, ar_lite_struct) \
opt_as axi_lite_if.ar_addr = ar_lite_struct.addr;
// prot not in interface!
opt_as axi_lite_if.ar_addr = ar_lite_struct.addr; \
opt_as axi_lite_if.ar_prot = ar_lite_struct.prot;
`define AXI_LITE_FROM_R(opt_as, axi_lite_if, r_lite_struct) \
opt_as axi_lite_if.r_data = r_lite_struct.data; \
opt_as axi_lite_if.r_resp = r_lite_struct.resp;
Expand Down Expand Up @@ -525,7 +527,7 @@
`define AXI_LITE_TO_AW(opt_as, aw_lite_struct, axi_lite_if) \
opt_as aw_lite_struct = '{ \
addr: axi_lite_if.aw_addr, \
prot: '0 \
prot: axi_lite_if.aw_prot \
};
// prot not in interface!
`define AXI_LITE_TO_W(opt_as, w_lite_struct, axi_lite_if) \
Expand All @@ -540,7 +542,7 @@
`define AXI_LITE_TO_AR(opt_as, ar_lite_struct, axi_lite_if) \
opt_as ar_lite_struct = '{ \
addr: axi_lite_if.ar_addr, \
prot: '0 \
prot: axi_lite_if.ar_prot \
};
`define AXI_LITE_TO_R(opt_as, r_lite_struct, axi_lite_if) \
opt_as r_lite_struct = '{ \
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20 changes: 12 additions & 8 deletions src/axi_intf.sv
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Expand Up @@ -347,6 +347,7 @@ interface AXI_LITE #(

// AW channel
addr_t aw_addr;
axi_pkg::prot_t aw_prot;
logic aw_valid;
logic aw_ready;

Expand All @@ -360,6 +361,7 @@ interface AXI_LITE #(
logic b_ready;

addr_t ar_addr;
axi_pkg::prot_t ar_prot;
logic ar_valid;
logic ar_ready;

Expand All @@ -369,18 +371,18 @@ interface AXI_LITE #(
logic r_ready;

modport Master (
output aw_addr, aw_valid, input aw_ready,
output aw_addr, aw_prot, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_valid, input ar_ready,
output ar_addr, ar_prot, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);

modport Slave (
input aw_addr, aw_valid, output aw_ready,
input aw_addr, aw_prot, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_valid, output ar_ready,
input ar_addr, ar_prot, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);

Expand All @@ -402,6 +404,7 @@ interface AXI_LITE_DV #(

// AW channel
addr_t aw_addr;
axi_pkg::prot_t aw_prot;
logic aw_valid;
logic aw_ready;

Expand All @@ -415,6 +418,7 @@ interface AXI_LITE_DV #(
logic b_ready;

addr_t ar_addr;
axi_pkg::prot_t ar_prot;
logic ar_valid;
logic ar_ready;

Expand All @@ -424,18 +428,18 @@ interface AXI_LITE_DV #(
logic r_ready;

modport Master (
output aw_addr, aw_valid, input aw_ready,
output aw_addr, aw_prot, aw_valid, input aw_ready,
output w_data, w_strb, w_valid, input w_ready,
input b_resp, b_valid, output b_ready,
output ar_addr, ar_valid, input ar_ready,
output ar_addr, ar_prot, ar_valid, input ar_ready,
input r_data, r_resp, r_valid, output r_ready
);

modport Slave (
input aw_addr, aw_valid, output aw_ready,
input aw_addr, aw_prot, aw_valid, output aw_ready,
input w_data, w_strb, w_valid, output w_ready,
output b_resp, b_valid, input b_ready,
input ar_addr, ar_valid, output ar_ready,
input ar_addr, ar_prot, ar_valid, output ar_ready,
output r_data, r_resp, r_valid, input r_ready
);

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64 changes: 41 additions & 23 deletions src/axi_test.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -43,12 +43,14 @@ package axi_test;

function void reset_master();
axi.aw_addr <= '0;
axi.aw_prot <= '0;
axi.aw_valid <= '0;
axi.w_valid <= '0;
axi.w_data <= '0;
axi.w_strb <= '0;
axi.b_ready <= '0;
axi.ar_valid <= '0;
axi.ar_prot <= '0;
axi.ar_addr <= '0;
axi.r_ready <= '0;
endfunction
Expand All @@ -74,14 +76,17 @@ package axi_test;

/// Issue a beat on the AW channel.
task send_aw (
input logic [AW-1:0] addr
input logic [AW-1:0] addr,
input prot_t prot
);
axi.aw_addr <= #TA addr;
axi.aw_prot <= #TA prot;
axi.aw_valid <= #TA 1;
cycle_start();
while (axi.aw_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.aw_addr <= #TA '0;
axi.aw_prot <= #TA '0;
axi.aw_valid <= #TA 0;
endtask

Expand Down Expand Up @@ -116,14 +121,17 @@ package axi_test;

/// Issue a beat on the AR channel.
task send_ar (
input logic [AW-1:0] addr
input logic [AW-1:0] addr,
input prot_t prot
);
axi.ar_addr <= #TA addr;
axi.ar_prot <= #TA prot;
axi.ar_valid <= #TA 1;
cycle_start();
while (axi.ar_ready != 1) begin cycle_end(); cycle_start(); end
cycle_end();
axi.ar_addr <= #TA '0;
axi.ar_prot <= #TA '0;
axi.ar_valid <= #TA 0;
endtask

Expand All @@ -145,12 +153,14 @@ package axi_test;

/// Wait for a beat on the AW channel.
task recv_aw (
output [AW-1:0] addr
output [AW-1:0] addr,
output prot_t prot
);
axi.aw_ready <= #TA 1;
cycle_start();
while (axi.aw_valid != 1) begin cycle_end(); cycle_start(); end
addr = axi.aw_addr;
prot = axi.aw_prot;
cycle_end();
axi.aw_ready <= #TA 0;
endtask
Expand Down Expand Up @@ -183,12 +193,14 @@ package axi_test;

/// Wait for a beat on the AR channel.
task recv_ar (
output [AW-1:0] addr
output [AW-1:0] addr,
output prot_t prot
);
axi.ar_ready <= #TA 1;
cycle_start();
while (axi.ar_valid != 1) begin cycle_end(); cycle_start(); end
addr = axi.ar_addr;
prot = axi.ar_prot;
cycle_end();
axi.ar_ready <= #TA 0;
endtask
Expand Down Expand Up @@ -1359,12 +1371,14 @@ package axi_test;

task automatic send_ars(input int unsigned n_reads);
automatic addr_t ar_addr;
automatic prot_t ar_prot;
repeat (n_reads) begin
rand_wait(AX_MIN_WAIT_CYCLES, AX_MAX_WAIT_CYCLES);
ar_addr = addr_t'($urandom_range(MIN_ADDR, MAX_ADDR));
ar_prot = prot_t'($urandom());
this.ar_queue.push_back(ar_addr);
$display("%0t %s> Send AR with ADDR: %h", $time(), this.name, ar_addr);
drv.send_ar(ar_addr);
$display("%0t %s> Send AR with ADDR: %h PROT: %b", $time(), this.name, ar_addr, ar_prot);
drv.send_ar(ar_addr, ar_prot);
end
endtask : send_ars

Expand All @@ -1377,18 +1391,20 @@ package axi_test;
ar_addr = this.ar_queue.pop_front();
rand_wait(RESP_MIN_WAIT_CYCLES, RESP_MAX_WAIT_CYCLES);
drv.recv_r(r_data, r_resp);
$display("%0t %s> Recv R with DATA: %h", $time(), this.name, r_data);
$display("%0t %s> Recv R with DATA: %h RESP: %0h", $time(), this.name, r_data, r_resp);
end
endtask : recv_rs

task automatic send_aws(input int unsigned n_writes);
automatic addr_t aw_addr;
automatic prot_t aw_prot;
repeat (n_writes) begin
rand_wait(AX_MIN_WAIT_CYCLES, AX_MAX_WAIT_CYCLES);
aw_addr = addr_t'($urandom_range(MIN_ADDR, MAX_ADDR));
aw_prot = prot_t'($urandom());
this.aw_queue.push_back(aw_addr);
$display("%0t %s> Send AW with ADDR: %h", $time(), this.name, aw_addr);
this.drv.send_aw(aw_addr);
$display("%0t %s> Send AW with ADDR: %h PROT: %b", $time(), this.name, aw_addr, aw_prot);
this.drv.send_aw(aw_addr, aw_prot);
this.b_queue.push_back(1'b1);
end
endtask : send_aws
Expand Down Expand Up @@ -1435,25 +1451,25 @@ package axi_test;
endtask

// write data to a specific address
task automatic write(input addr_t w_addr, input data_t w_data, input strb_t w_strb,
output axi_pkg::resp_t b_resp);
$display("%0t %s> Write to ADDR: %h, DATA: %h, STRB: %h",
$time(), this.name, w_addr, w_data, w_strb);
task automatic write(input addr_t w_addr, input prot_t w_prot, input data_t w_data,
input strb_t w_strb, output axi_pkg::resp_t b_resp);
$display("%0t %s> Write to ADDR: %h, PROT: %b DATA: %h, STRB: %h",
$time(), this.name, w_addr, w_prot, w_data, w_strb);
fork
this.drv.send_aw(w_addr);
this.drv.send_aw(w_addr, w_prot);
this.drv.send_w(w_data, w_strb);
join
this.drv.recv_b(b_resp);
$display("%0t %s> Recieved write response from ADDR: %h RESP: %h",
$display("%0t %s> Received write response from ADDR: %h RESP: %h",
$time(), this.name, w_addr, b_resp);
endtask : write

// read data from a specific location
task automatic read(input addr_t r_addr,
task automatic read(input addr_t r_addr, input prot_t r_prot,
output data_t r_data, output axi_pkg::resp_t r_resp);
$display("%0t %s> Read from ADDR: %h",
$time(), this.name, r_addr);
this.drv.send_ar(r_addr);
$display("%0t %s> Read from ADDR: %h PROT: %b",
$time(), this.name, r_addr, r_prot);
this.drv.send_ar(r_addr, r_prot);
this.drv.recv_r(r_data, r_resp);
$display("%0t %s> Recieved read response from ADDR: %h DATA: %h RESP: %h",
$time(), this.name, r_addr, r_data, r_resp);
Expand Down Expand Up @@ -1517,9 +1533,10 @@ package axi_test;
task automatic recv_ars();
forever begin
automatic addr_t ar_addr;
automatic prot_t ar_prot;
rand_wait(AX_MIN_WAIT_CYCLES, AX_MAX_WAIT_CYCLES);
this.drv.recv_ar(ar_addr);
$display("%0t %s> Recv AR with ADDR: %h", $time(), this.name, ar_addr);
this.drv.recv_ar(ar_addr, ar_prot);
$display("%0t %s> Recv AR with ADDR: %h PROT: %b", $time(), this.name, ar_addr, ar_prot);
this.ar_queue.push_back(ar_addr);
end
endtask : recv_ars
Expand All @@ -1541,9 +1558,10 @@ package axi_test;
task automatic recv_aws();
forever begin
automatic addr_t aw_addr;
automatic prot_t aw_prot;
rand_wait(AX_MIN_WAIT_CYCLES, AX_MAX_WAIT_CYCLES);
this.drv.recv_aw(aw_addr);
$display("%0t %s> Recv AW with ADDR: %h", $time(), this.name, aw_addr);
this.drv.recv_aw(aw_addr, aw_prot);
$display("%0t %s> Recv AW with ADDR: %h PROT: %b", $time(), this.name, aw_addr, aw_prot);
this.aw_queue.push_back(aw_addr);
end
endtask : recv_aws
Expand Down
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