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x86/hpet: Separate counter check out of clocksource register code
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The init code checks whether the HPET counter works late in the init
function when the clocksource is registered. That should happen right with
the other sanity checks.

Split it into a separate validation function and move it to the other
sanity checks.

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Ingo Molnar <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Ricardo Neri <[email protected]>
Cc: Ashok Raj <[email protected]>
Cc: Andi Kleen <[email protected]>
Cc: Suravee Suthikulpanit <[email protected]>
Cc: Stephane Eranian <[email protected]>
Cc: Ravi Shankar <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
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KAGA-KOKO committed Jun 27, 2019
1 parent 6bdec41 commit 3222daf
Showing 1 changed file with 31 additions and 34 deletions.
65 changes: 31 additions & 34 deletions arch/x86/kernel/hpet.c
Original file line number Diff line number Diff line change
Expand Up @@ -809,38 +809,6 @@ static struct clocksource clocksource_hpet = {
.resume = hpet_resume_counter,
};

static int __init hpet_clocksource_register(void)
{
u64 start, now;
u64 t1;

/* Start the counter */
hpet_restart_counter();

/* Verify whether hpet counter works */
t1 = hpet_readl(HPET_COUNTER);
start = rdtsc();

/*
* We don't know the TSC frequency yet, but waiting for
* 200000 TSC cycles is safe:
* 4 GHz == 50us
* 1 GHz == 200us
*/
do {
rep_nop();
now = rdtsc();
} while ((now - start) < 200000UL);

if (t1 == hpet_readl(HPET_COUNTER)) {
pr_warn("Counter not counting. HPET disabled\n");
return -ENODEV;
}

clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
return 0;
}

/*
* AMD SB700 based systems with spread spectrum enabled use a SMM based
* HPET emulation to provide proper frequency setting.
Expand Down Expand Up @@ -869,6 +837,32 @@ static bool __init hpet_cfg_working(void)
return false;
}

static bool __init hpet_counting(void)
{
u64 start, now, t1;

hpet_restart_counter();

t1 = hpet_readl(HPET_COUNTER);
start = rdtsc();

/*
* We don't know the TSC frequency yet, but waiting for
* 200000 TSC cycles is safe:
* 4 GHz == 50us
* 1 GHz == 200us
*/
do {
rep_nop();
now = rdtsc();
} while ((now - start) < 200000UL);

if (t1 == hpet_readl(HPET_COUNTER)) {
pr_warn("Counter not counting. HPET disabled\n");
return false;
}
return true;
}

/**
* hpet_enable - Try to setup the HPET timer. Returns 1 on success.
Expand All @@ -890,6 +884,10 @@ int __init hpet_enable(void)
if (!hpet_cfg_working())
goto out_nohpet;

/* Validate that the counter is counting */
if (!hpet_counting())
goto out_nohpet;

/*
* Read the period and check for a sane value:
*/
Expand Down Expand Up @@ -948,8 +946,7 @@ int __init hpet_enable(void)
}
hpet_print_config();

if (hpet_clocksource_register())
goto out_nohpet;
clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);

if (id & HPET_ID_LEGSUP) {
hpet_legacy_clockevent_register();
Expand Down

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