Xv6 for RISC-V

The Xr0 Verifier for C

Dataset of Rust source code repositories

3-stage RV32IMACZb* processor with debug

Defines the Rust borrow checker.

Pragmatic microkernel-based OS with fully asynchronous I/O

Cross-platform Rust rewrite of the GNU coreutils

A new markup-based typesetting system that is powerful and easy to learn.

A precise specification for "Rust lite / MIR plus"

The Rust specification

GPGPU microprocessor architecture

A minimal GPU design in Verilog to learn how GPUs work from the ground up

DRAMSim2: A cycle accurate DRAM simulator

XLS: Accelerated HW Synthesis

A 32-bit RISC-V Processor Designed with High-Level Synthesis

revng: the core repository of the rev.ng project

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Blazingly 🔥 fast 🚀 memory vulnerabilities, written in 100% safe Rust. 🦀

A key remapping daemon for linux.

easylkb - Easy Linux Kernel Builder

A curated list of awesome projects related to eBPF.

⚙️ A curated list of static analysis (SAST) tools and linters for all programming languages, config files, build tools, and more. The focus is on tools which improve code quality.

Bao, a Lightweight Static Partitioning Hypervisor

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

F-Stack is an user space network development kit with high performance based on DPDK, FreeBSD TCP/IP stack and coroutine API.

A tiny Open POWER ISA softcore written in VHDL 2008

Safe collections written in stable Rust, based on GhostCell and StaticRc.

Hardware Description Languages

A project for generating C bindings from Rust code

Risc-V hypervisor for TEE development