mmc: cavium-octeon: Fix interrupt enable code

OCTEON SoCs with CIU3 do not have interrupt masking local to the MMC bus interface. Unfortunately, some even have a diagnostic register at the same address of the enable register, which causes the interrupts to fire immediately if stored to, thus breaking the driver. The proper action on these SoCs is not to touch this register. Fixes: 01d9584 ("mmc: cavium: Add MMC support for Octeon SOCs.") Signed-off-by: David Daney <[email protected]> [[email protected]: removed point after subject line] Signed-off-by: Jan Glauber <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
jbg · May 19, 2017 · aca6934 · aca6934
1 parent bae3dee
commit aca6934
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/drivers/mmc/host/cavium-octeon.c b/drivers/mmc/host/cavium-octeon.c
@@ -108,7 +108,7 @@ static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
 static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
 {
 	writeq(val, host->base + MIO_EMM_INT(host));
-	if (!host->dma_active || (host->dma_active && !host->has_ciu3))
+	if (!host->has_ciu3)
 		writeq(val, host->base + MIO_EMM_INT_EN(host));
 }