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Merge tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kern…
…el/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "For this kernel cycle I managed an immutable branch for the PEF2256 WAN framer that has some pin control portions. It already landed in your tree through the net pull request but here it is mentioned again. The most interesting is perhaps the Samsung Exynos subdrivers for the Tensor SoC used in Google Pixel 6 and the ExynosAuto subdriver for automotive. Along with the earlier merged Tesla FSD subdriver it shows some of the versatile uses of the Samsung Exynos silicon. It is also used in the latest version of Axis Communications ARTPEC chips so it is a very widely deployed SoC family. We also have the Intel Meteor Lake SoC which I think is for laptops. It's a pretty interesting chip with Xe graphics and integrated PCH. Core changes: - A new PINCTRL_GROUP_DESC() infrastructure macro is added and used in different drivers, generic group description struct group_desc is now used all over the place. New drivers: - New driver for the Texas Instruments TPS6494 Power Management IC. - New driver for the Lantic PEF2256 framer pin multiplexer. This IC has some pins that can be reconfigured in different ways. The actual driver comes on an immutable branch with the net WAN parts, the IC is some latest-and-greatest serial line funnel for e.g. wireless access points. - New subdriver for the Samsung Exynos Auto V920 pin controller, used for automotive applications. - New subdriver for the Samsung "GS101" SoC pin controller, this is the Google "Tensor" SoC used in the Google Pixel 6. - New subdriver for the Intel Meteor Point SoC pin controller. - New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS pin controllers. - New subdriver for the Qualcomm X1E80100 top level (TLMM) pin controller. - New subdriver for the Qualcomm SM4450 top level (TLMM) pin controller. - The "single" pin controller now supports the Texas Instruments J7200 SoC. Improvements: - Intel has created a new (Intel-)generic pin controller driver that is now used by all contemporary Intel platforms. - Intel is now also making use of some cleanup helpers. - Enble 910 Ohm bias in the Intel Tangier driver. - The Samsung driver now suppors irq_set_affinity() in it's IRQ chip giving support for non wake up external gpio interrupts" * tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits) pinctrl: samsung: constify iomem pointers pinctrl: cy8c95x0: Cache muxed registers dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp pinctrl: qcom: lpass-lpi: remove duplicated include dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent dt-bindings: pinctrl: qcom: drop common properties dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom: create common LPASS LPI schema pinctrl: qcom: sm4450: dd SM4450 pinctrl driver dt-bindings: pinctrl: qcom: Add SM4450 pinctrl dt-bindings: pinctrl: qcom,pmic-mpp: clean up example pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins pinctrl: renesas: rzg2l: Add output enable support ...
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Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-common.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Qualcomm SoC LPASS LPI TLMM Common Properties | ||
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maintainers: | ||
- Bjorn Andersson <[email protected]> | ||
- Srinivas Kandagatla <[email protected]> | ||
- Krzysztof Kozlowski <[email protected]> | ||
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description: | ||
Common properties for the Top Level Mode Multiplexer pin controllers in the | ||
Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm SoCs. | ||
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properties: | ||
gpio-controller: true | ||
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"#gpio-cells": | ||
description: | ||
Specifying the pin number and flags, as defined in | ||
include/dt-bindings/gpio/gpio.h | ||
const: 2 | ||
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gpio-ranges: | ||
maxItems: 1 | ||
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required: | ||
- gpio-controller | ||
- "#gpio-cells" | ||
- gpio-ranges | ||
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allOf: | ||
- $ref: pinctrl.yaml# | ||
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additionalProperties: true | ||
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$defs: | ||
qcom-tlmm-state: | ||
properties: | ||
drive-strength: | ||
enum: [2, 4, 6, 8, 10, 12, 14, 16] | ||
default: 2 | ||
description: | ||
Selects the drive strength for the specified pins, in mA. | ||
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slew-rate: | ||
enum: [0, 1, 2, 3] | ||
default: 0 | ||
description: | | ||
0: No adjustments | ||
1: Higher Slew rate (faster edges) | ||
2: Lower Slew rate (slower edges) | ||
3: Reserved (No adjustments) | ||
bias-bus-hold: true | ||
bias-pull-down: true | ||
bias-pull-up: true | ||
bias-disable: true | ||
input-enable: true | ||
output-high: true | ||
output-low: true | ||
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required: | ||
- pins | ||
- function | ||
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allOf: | ||
- $ref: pincfg-node.yaml# | ||
- $ref: pinmux-node.yaml# | ||
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additionalProperties: true | ||
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