STRD and LDRD require ARMv5TE, not just ARMv5T.

See http://llvm.org/PR4687 for more info and links. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80244 91177308-0d34-0410-b5e6-96231b3b80d8
jcnm · Aug 27, 2009 · bf16f1d · bf16f1d
1 parent 6205048
commit bf16f1d
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
@@ -767,7 +767,7 @@ let mayLoad = 1 in {
 // Load doubleword
 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
                  IIC_iLoadr, "ldr", "d $dst1, $addr",
-                 []>, Requires<[IsARM, HasV5T]>;
+                 []>, Requires<[IsARM, HasV5TE]>;
 
 // Indexed loads
 def LDR_PRE  : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
@@ -829,7 +829,7 @@ def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
 let mayStore = 1 in
 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
                StMiscFrm, IIC_iStorer,
-               "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
+               "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
 
 // Indexed stores
 def STR_PRE  : AI2stwpr<(outs GPR:$base_wb),