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  • Rift2Core Public

    Forked from whutddk/Rift2Core

    Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

    Scala Apache License 2.0 Updated Jan 31, 2022

  • Surelog Public

    Forked from chipsalliance/Surelog

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    C++ Apache License 2.0 Updated Dec 16, 2021

  • riscv-gnu-toolchain Public

    Forked from riscv-collab/riscv-gnu-toolchain

    GNU toolchain for RISC-V, including GCC

    C Other Updated Oct 8, 2021

  • OpenLane Public

    Forked from efabless/OpenLane

    NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Mag…

    Verilog Apache License 2.0 Updated Jul 8, 2021

  • livehd Public

    Forked from masc-ucsc/livehd

    Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

    Verilog Other Updated Jun 19, 2021

  • SOFA Public

    Forked from lnis-uofu/SOFA

    SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

    Verilog MIT License Updated Apr 4, 2021

  • yosys-examples Public

    Forked from nkkav/yosys-examples

    Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)

    Verilog Updated Apr 13, 2020

  • chipyard Public

    Forked from ucb-bar/chipyard

    An Agile Chisel-Based SoC Design Framework

    Scala Other Updated Nov 17, 2019

  • QGnomePlatform Public

    Forked from FedoraQt/QGnomePlatform

    QPlatformTheme for a better Qt application inclusion in GNOME

    C++ GNU Lesser General Public License v2.1 Updated Nov 18, 2018

  • iso-profiles Public

    Forked from oberon-manjaro/iso-profiles

    This is a mirror repo of iso-profiles

    Shell Updated Jul 2, 2018

  • OpenFPGA Public

    Forked from haojunliu/OpenFPGA

    OpenFPGA

    Verilog BSD 2-Clause "Simplified" License Updated Mar 12, 2018

  • manifest Public

    Forked from niftich/manifest
    Shell Other Updated Jun 24, 2017

  • SYMPL-GP-GPU-Compute-Engines Public

    Forked from jerry-D/SYMPL-GP-GPU-Compute-Engines

    Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for IEEE754-2008 compliant, 32-bit si…

    Verilog Other Updated May 2, 2016