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Fix whitespace and semicolons in macro calls
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andreaskurth committed Mar 13, 2020
1 parent d649e6a commit 5a4dd25
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1 change: 1 addition & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
### Changed

### Fixed
- Remove whitespace in and semicolon after macro calls.


## 0.16.0 - 2020-03-11
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28 changes: 14 additions & 14 deletions include/axi/assign.svh
Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,9 @@
// `src` was the master of `dst`.
//
// Usage Example:
// `AXI_ASSIGN(slv, mst);
// `AXI_ASSIGN_AW(dst, src);
// `AXI_ASSIGN_R(dst, src);
// `AXI_ASSIGN(slv, mst)
// `AXI_ASSIGN_AW(dst, src)
// `AXI_ASSIGN_R(dst, src)
`define AXI_ASSIGN_AW(dst, src) \
assign dst.aw_id = src.aw_id; \
assign dst.aw_addr = src.aw_addr; \
Expand Down Expand Up @@ -167,7 +167,7 @@
//
// Usage Example:
// always_comb begin
// `AXI_SET_FROM_REQ(my_if, my_req_struct);
// `AXI_SET_FROM_REQ(my_if, my_req_struct)
// end
`define AXI_SET_FROM_AW(axi_if, aw_struct) `AXI_FROM_AW(, axi_if, aw_struct)
`define AXI_SET_FROM_W(axi_if, w_struct) `AXI_FROM_W(, axi_if, w_struct)
Expand All @@ -192,7 +192,7 @@
// `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// `AXI_ASSIGN_FROM_REQ(my_if, my_req_struct);
// `AXI_ASSIGN_FROM_REQ(my_if, my_req_struct)
`define AXI_ASSIGN_FROM_AW(axi_if, aw_struct) `AXI_FROM_AW(assign, axi_if, aw_struct)
`define AXI_ASSIGN_FROM_W(axi_if, w_struct) `AXI_FROM_W(assign, axi_if, w_struct)
`define AXI_ASSIGN_FROM_B(axi_if, b_struct) `AXI_FROM_B(assign, axi_if, b_struct)
Expand Down Expand Up @@ -292,7 +292,7 @@
//
// Usage Example:
// always_comb begin
// `AXI_SET_TO_REQ(my_req_struct, my_if);
// `AXI_SET_TO_REQ(my_req_struct, my_if)
// end
`define AXI_SET_TO_AW(aw_struct, axi_if) `AXI_TO_AW(, aw_struct, axi_if)
`define AXI_SET_TO_W(w_struct, axi_if) `AXI_TO_W(, w_struct, axi_if)
Expand All @@ -318,7 +318,7 @@
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// `AXI_ASSIGN_TO_REQ(my_req_struct, my_if);
// `AXI_ASSIGN_TO_REQ(my_req_struct, my_if)
`define AXI_ASSIGN_TO_AW(aw_struct, axi_if) `AXI_TO_AW(assign, aw_struct, axi_if)
`define AXI_ASSIGN_TO_W(w_struct, axi_if) `AXI_TO_W(assign, w_struct, axi_if)
`define AXI_ASSIGN_TO_B(b_struct, axi_if) `AXI_TO_B(assign, b_struct, axi_if)
Expand All @@ -339,9 +339,9 @@
// if `src` was the master of `dst`.
//
// Usage Example:
// `AXI_LITE_ASSIGN(slv, mst);
// `AXI_LITE_ASSIGN_AW(dst, src);
// `AXI_LITE_ASSIGN_R(dst, src);
// `AXI_LITE_ASSIGN(slv, mst)
// `AXI_LITE_ASSIGN_AW(dst, src)
// `AXI_LITE_ASSIGN_R(dst, src)
`define AXI_LITE_ASSIGN_AW(dst, src) \
assign dst.aw_addr = src.aw_addr; \
assign dst.aw_valid = src.aw_valid; \
Expand Down Expand Up @@ -425,7 +425,7 @@
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_FROM_REQ(my_if, my_req_struct);
// `AXI_LITE_SET_FROM_REQ(my_if, my_req_struct)
// end
`define AXI_LITE_SET_FROM_AW(axi_if, aw_struct) `AXI_LITE_FROM_AW(, axi_if, aw_struct)
`define AXI_LITE_SET_FROM_W(axi_if, w_struct) `AXI_LITE_FROM_W(, axi_if, w_struct)
Expand All @@ -450,7 +450,7 @@
// ready) of the `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// `AXI_LITE_ASSIGN_FROM_REQ(my_if, my_req_struct);
// `AXI_LITE_ASSIGN_FROM_REQ(my_if, my_req_struct)
`define AXI_LITE_ASSIGN_FROM_AW(axi_if, aw_struct) `AXI_LITE_FROM_AW(assign, axi_if, aw_struct)
`define AXI_LITE_ASSIGN_FROM_W(axi_if, w_struct) `AXI_LITE_FROM_W(assign, axi_if, w_struct)
`define AXI_LITE_ASSIGN_FROM_B(axi_if, b_struct) `AXI_LITE_FROM_B(assign, axi_if, b_struct)
Expand Down Expand Up @@ -525,7 +525,7 @@
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_TO_REQ(my_req_struct, my_if);
// `AXI_LITE_SET_TO_REQ(my_req_struct, my_if)
// end
`define AXI_LITE_SET_TO_AW(aw_struct, axi_if) `AXI_LITE_TO_AW(, aw_struct, axi_if)
`define AXI_LITE_SET_TO_W(w_struct, axi_if) `AXI_LITE_TO_W(, w_struct, axi_if)
Expand All @@ -551,7 +551,7 @@
// and R valid and AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// `AXI_LITE_ASSIGN_TO_REQ(my_req_struct, my_if);
// `AXI_LITE_ASSIGN_TO_REQ(my_req_struct, my_if)
`define AXI_LITE_ASSIGN_TO_AW(aw_struct, axi_if) `AXI_LITE_TO_AW(assign, aw_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_W(w_struct, axi_if) `AXI_LITE_TO_W(assign, w_struct, axi_if)
`define AXI_LITE_ASSIGN_TO_B(b_struct, axi_if) `AXI_LITE_TO_B(assign, b_struct, axi_if)
Expand Down
28 changes: 14 additions & 14 deletions include/axi/typedef.svh
Original file line number Diff line number Diff line change
Expand Up @@ -21,13 +21,13 @@
// AXI4+ATOP Channel and Request/Response Structs
//
// Usage Example:
// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_user_t);
// `AXI_TYPEDEF_W_CHAN_T (axi_w_t, axi_data_t, axi_strb_t, axi_user_t);
// `AXI_TYPEDEF_B_CHAN_T (axi_b_t, axi_id_t, axi_user_t);
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t);
// `AXI_TYPEDEF_R_CHAN_T (axi_r_t, axi_data_t, axi_id_t, axi_user_t);
// `AXI_TYPEDEF_REQ_T (axi_req_t, axi_aw_t, axi_w_t, axi_ar_t);
// `AXI_TYPEDEF_RESP_T (axi_resp_t, axi_b_t, axi_r_t);
// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t)
// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t)
// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t)
`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
Expand Down Expand Up @@ -106,13 +106,13 @@
// AXI-Lite (4+Prot) Channel and Request/Response Structs
//
// Usage Example:
// `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_aw_t, axi_lite_addr_t);
// `AXI_LITE_TYPEDEF_W_CHAN_T (axi_lite_w_t, axi_lite_data_t, axi_lite_strb_t);
// `AXI_LITE_TYPEDEF_B_CHAN_T (axi_lite_b_t);
// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t);
// `AXI_LITE_TYPEDEF_R_CHAN_T (axi_lite_r_t, axi_lite_data_t);
// `AXI_LITE_TYPEDEF_REQ_T (axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t);
// `AXI_LITE_TYPEDEF_RESP_T (axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t);
// `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_aw_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_W_CHAN_T(axi_lite_w_t, axi_lite_data_t, axi_lite_strb_t)
// `AXI_LITE_TYPEDEF_B_CHAN_T(axi_lite_b_t)
// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t)
// `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t)
// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t)
`define AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t) \
typedef struct packed { \
addr_t addr; \
Expand Down
22 changes: 11 additions & 11 deletions src/axi_atop_filter.sv
Original file line number Diff line number Diff line change
Expand Up @@ -382,22 +382,22 @@ module axi_atop_filter_intf #(
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;

`AXI_TYPEDEF_AW_CHAN_T ( aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T ( b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T ( ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T ( r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T ( req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T ( resp_t, b_chan_t, r_chan_t)
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;

`AXI_ASSIGN_TO_REQ ( slv_req, slv )
`AXI_ASSIGN_FROM_RESP ( slv, slv_resp )
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)

`AXI_ASSIGN_FROM_REQ ( mst , mst_req )
`AXI_ASSIGN_TO_RESP ( mst_resp, mst )
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)

axi_atop_filter #(
.AxiIdWidth ( AXI_ID_WIDTH ),
Expand Down
24 changes: 12 additions & 12 deletions src/axi_burst_splitter.sv
Original file line number Diff line number Diff line change
Expand Up @@ -52,11 +52,11 @@ module axi_burst_splitter #(
typedef logic [IdWidth-1:0] id_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t, user_t);
`AXI_TYPEDEF_B_CHAN_T ( b_chan_t, id_t, user_t);
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_R_CHAN_T ( r_chan_t, data_t, id_t, user_t);
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)

// Demultiplex between supported and unsupported transactions.
req_t act_req, unsupported_req;
Expand Down Expand Up @@ -304,10 +304,10 @@ module axi_burst_splitter #(
// --------------------------------------------------
// Flip-Flops
// --------------------------------------------------
`FFARN ( b_err_q , b_err_d, 1'b0, clk_i, rst_ni )
`FFARN ( b_state_q, b_state_d, BReady, clk_i, rst_ni )
`FFARN ( r_last_q , r_last_d, 1'b0, clk_i, rst_ni )
`FFARN ( r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni )
`FFARN(b_err_q, b_err_d, 1'b0, clk_i, rst_ni)
`FFARN(b_state_q, b_state_d, BReady, clk_i, rst_ni)
`FFARN(r_last_q, r_last_d, 1'b0, clk_i, rst_ni)
`FFARN(r_state_q, r_state_d, RFeedthrough, clk_i, rst_ni)

// --------------------------------------------------
// Assumptions and assertions
Expand Down Expand Up @@ -448,8 +448,8 @@ module axi_burst_splitter_ax_chan #(
end

// registers
`FFARN ( ax_q, ax_d, '0, clk_i, rst_ni )
`FFARN ( state_q, state_d, Idle, clk_i, rst_ni )
`FFARN(ax_q, ax_d, '0, clk_i, rst_ni)
`FFARN(state_q, state_d, Idle, clk_i, rst_ni)
endmodule

module axi_burst_splitter_counters #(
Expand Down Expand Up @@ -561,7 +561,7 @@ module axi_burst_splitter_counters #(
end

// registers
`FFARN ( err_q, err_d, '0, clk_i, rst_ni )
`FFARN(err_q, err_d, '0, clk_i, rst_ni)

`ifndef VERILATOR
// pragma translate_off
Expand Down
22 changes: 11 additions & 11 deletions src/axi_cdc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -153,22 +153,22 @@ module axi_cdc_intf #(
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T ( aw_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t, user_t);
`AXI_TYPEDEF_B_CHAN_T ( b_chan_t, id_t, user_t);
`AXI_TYPEDEF_AR_CHAN_T ( ar_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_R_CHAN_T ( r_chan_t, data_t, id_t, user_t);
`AXI_TYPEDEF_REQ_T ( req_t, aw_chan_t, w_chan_t, ar_chan_t);
`AXI_TYPEDEF_RESP_T ( resp_t, b_chan_t, r_chan_t);
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

req_t src_req, dst_req;
resp_t src_resp, dst_resp;

`AXI_ASSIGN_TO_REQ ( src_req, src );
`AXI_ASSIGN_FROM_RESP ( src, src_resp );
`AXI_ASSIGN_TO_REQ(src_req, src)
`AXI_ASSIGN_FROM_RESP(src, src_resp)

`AXI_ASSIGN_FROM_REQ ( dst , dst_req );
`AXI_ASSIGN_TO_RESP ( dst_resp, dst );
`AXI_ASSIGN_FROM_REQ(dst, dst_req)
`AXI_ASSIGN_TO_RESP(dst_resp, dst)

axi_cdc #(
.aw_chan_t ( aw_chan_t ),
Expand Down
36 changes: 18 additions & 18 deletions src/axi_cut.sv
Original file line number Diff line number Diff line change
Expand Up @@ -138,22 +138,22 @@ module axi_cut_intf #(
typedef logic [DATA_WIDTH/8-1:0] strb_t;
typedef logic [USER_WIDTH-1:0] user_t;

`AXI_TYPEDEF_AW_CHAN_T ( aw_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t, user_t);
`AXI_TYPEDEF_B_CHAN_T ( b_chan_t, id_t, user_t);
`AXI_TYPEDEF_AR_CHAN_T ( ar_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_R_CHAN_T ( r_chan_t, data_t, id_t, user_t);
`AXI_TYPEDEF_REQ_T ( req_t, aw_chan_t, w_chan_t, ar_chan_t);
`AXI_TYPEDEF_RESP_T ( resp_t, b_chan_t, r_chan_t);
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;

`AXI_ASSIGN_TO_REQ ( slv_req, in );
`AXI_ASSIGN_FROM_RESP ( in, slv_resp );
`AXI_ASSIGN_TO_REQ(slv_req, in)
`AXI_ASSIGN_FROM_RESP(in, slv_resp)

`AXI_ASSIGN_FROM_REQ ( out , mst_req );
`AXI_ASSIGN_TO_RESP ( mst_resp, out );
`AXI_ASSIGN_FROM_REQ(out, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, out)

axi_cut #(
.Bypass ( BYPASS ),
Expand Down Expand Up @@ -212,13 +212,13 @@ module axi_lite_cut_intf #(
typedef logic [DATA_WIDTH-1:0] data_t;
typedef logic [DATA_WIDTH/8-1:0] strb_t;

`AXI_LITE_TYPEDEF_AW_CHAN_T ( aw_chan_t, addr_t )
`AXI_LITE_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T ( b_chan_t )
`AXI_LITE_TYPEDEF_AR_CHAN_T ( ar_chan_t, addr_t )
`AXI_LITE_TYPEDEF_R_CHAN_T ( r_chan_t, data_t )
`AXI_LITE_TYPEDEF_REQ_T ( req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T ( resp_t, b_chan_t, r_chan_t)
`AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t)
`AXI_LITE_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t)
`AXI_LITE_TYPEDEF_B_CHAN_T(b_chan_t)
`AXI_LITE_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t)
`AXI_LITE_TYPEDEF_R_CHAN_T(r_chan_t, data_t)
`AXI_LITE_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_LITE_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;
Expand Down
22 changes: 11 additions & 11 deletions src/axi_delayer.sv
Original file line number Diff line number Diff line change
Expand Up @@ -144,22 +144,22 @@ module axi_delayer_intf #(
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;

`AXI_TYPEDEF_AW_CHAN_T ( aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T ( b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T ( ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T ( r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T ( req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T ( resp_t, b_chan_t, r_chan_t)
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

req_t slv_req, mst_req;
resp_t slv_resp, mst_resp;

`AXI_ASSIGN_TO_REQ ( slv_req, slv )
`AXI_ASSIGN_FROM_RESP ( slv, slv_resp )
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)

`AXI_ASSIGN_FROM_REQ ( mst , mst_req )
`AXI_ASSIGN_TO_RESP ( mst_resp, mst )
`AXI_ASSIGN_FROM_REQ(mst, mst_req)
`AXI_ASSIGN_TO_RESP(mst_resp, mst)

axi_delayer #(
.aw_chan_t ( aw_chan_t ),
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22 changes: 11 additions & 11 deletions src/axi_demux.sv
Original file line number Diff line number Diff line change
Expand Up @@ -682,25 +682,25 @@ module axi_demux_intf #(
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T( aw_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_W_CHAN_T ( w_chan_t, data_t, strb_t, user_t);
`AXI_TYPEDEF_B_CHAN_T ( b_chan_t, id_t, user_t);
`AXI_TYPEDEF_AR_CHAN_T( ar_chan_t, addr_t, id_t, user_t);
`AXI_TYPEDEF_R_CHAN_T ( r_chan_t, data_t, id_t, user_t);
`AXI_TYPEDEF_REQ_T ( req_t, aw_chan_t, w_chan_t, ar_chan_t);
`AXI_TYPEDEF_RESP_T ( resp_t, b_chan_t, r_chan_t) ;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

req_t slv_req;
resp_t slv_resp;
req_t [NO_MST_PORTS-1:0] mst_req;
resp_t [NO_MST_PORTS-1:0] mst_resp;

`AXI_ASSIGN_TO_REQ ( slv_req, slv )
`AXI_ASSIGN_FROM_RESP ( slv, slv_resp )
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)

for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports
`AXI_ASSIGN_FROM_REQ ( mst[i] , mst_req[i] )
`AXI_ASSIGN_TO_RESP ( mst_resp[i], mst[i] )
`AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i])
`AXI_ASSIGN_TO_RESP(mst_resp[i], mst[i])
end

axi_demux #(
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