core: crypto: arm32: add counter increment in ce_aes_ctr_encrypt()

Commit 628a9a1 ("ltc: ctr: improve performance") reveals a bug in
the Aarch32 accelerated crypto code (AES CTR mode), which causes xtest
9159 to fail with some invalid buffer content: encrypting 96 bytes of
data in one pass does not yield the same result than encrypting 3 * 32
bytes. The problem is fixed by adding a missing counter increment in
ce_aes_ctr_encrypt().

Fixes: 9ff4f2c ("arm32: AES using ARMv8-A cryptographic extensions")
Signed-off-by: Jerome Forissier <[email protected]>
Tested-by: Jerome Forissier <[email protected]> (HiKey960)
Acked-by: Joakim Bech <[email protected]>
Acked-by: Jens Wiklander <[email protected]>

core/lib/libtomcrypt/src/ciphers/aes_modes_armv8a_ce_a32.S

@@ -296,6 +296,7 @@ ce_aes_ctr_encrypt:
 .Lctrloop3x:
 	subs		r4, r4, #3
 	bmi		.Lctr1x
+	add		r6, r6, #1
 	vmov		q0, q6
 	vmov		q1, q6
 	rev		ip, r6