Skip to content

Commit

Permalink
indentation with tab
Browse files Browse the repository at this point in the history
  • Loading branch information
@aquynh
aquynh committed May 8, 2014
1 parent 336bf29 commit 42706a3
Show file tree
Hide file tree
Showing 16 changed files with 182 additions and 182 deletions.
2 changes: 1 addition & 1 deletion SStream.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ void SStream_concat(SStream *ss, const char *fmt, ...)
{
#ifndef CAPSTONE_DIET
va_list ap;
int ret = 0;
int ret = 0;
va_start(ap, fmt);
ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
va_end(ap);
Expand Down
20 changes: 11 additions & 9 deletions arch/AArch64/AArch64BaseInfo.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@

/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <[email protected]>, 2013> */

#define _CRT_SECURE_NO_WARNINGS
#include "../../utils.h"

Expand All @@ -39,7 +40,7 @@ char *NamedImmMapper_toString(NamedImmMapper *N, uint32_t Value, bool *Valid)
// return true if s1 == lower(f2), and false otherwise
static bool compare_lower_str(char *s1, char *s2)
{
bool res;
bool res;
char *lower = cs_strdup(s2), *c;
for (c = lower; *c; c++)
*c = (char)tolower((int) *c);
Expand Down Expand Up @@ -75,7 +76,7 @@ static char *utostr(uint64_t X, bool isNeg)
{
char Buffer[22];
char *BufPtr = Buffer+21;
char *result = NULL;
char *result = NULL;

Buffer[21] = '\0';
if (X == 0) *--BufPtr = '0'; // Handle special case...
Expand Down Expand Up @@ -573,10 +574,11 @@ static NamedImmMapper_Mapping SysRegPairs[] = {
// result must be a big enough buffer: 128 bytes is more than enough
void SysRegMapper_toString(SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
{
int dummy = 0;
uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
char *Op1S = NULL, *CRnS = NULL, *CRmS = NULL, *Op2S = NULL;
int dummy = 0;
uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
char *Op1S = NULL, *CRnS = NULL, *CRmS = NULL, *Op2S = NULL;
unsigned i;

for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
if (SysRegPairs[i].Value == Bits) {
*Valid = true;
Expand Down Expand Up @@ -886,7 +888,7 @@ static NamedImmMapper_Mapping MRSPairs[] = {
};

SysRegMapper AArch64_MRSMapper = {
NULL,
NULL,
MRSPairs,
ARR_SIZE(MRSPairs),
};
Expand All @@ -911,7 +913,7 @@ static NamedImmMapper_Mapping MSRPairs[] = {

SysRegMapper AArch64_MSRMapper = {
NULL,
MSRPairs,
MSRPairs,
ARR_SIZE(MSRPairs),
};

Expand Down Expand Up @@ -941,8 +943,8 @@ bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm)
uint32_t N = Bits >> 12;
uint32_t ImmR = (Bits >> 6) & 0x3f;
uint32_t ImmS = Bits & 0x3f;
uint64_t Mask = 0, WidthMask = 0;
unsigned i = 0;
uint64_t Mask = 0, WidthMask = 0;
unsigned i = 0;
int Width = 0, Num1s = 0, Rotation = 0;

// N=1 encodes a 64-bit replication and is invalid for the 32-bit
Expand Down
15 changes: 7 additions & 8 deletions arch/AArch64/AArch64Disassembler.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,14 +32,12 @@
// Forward-declarations used in the auto-generated files.
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);
static DecodeStatus
DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);

static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);
static DecodeStatus
DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder);

static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
Expand Down Expand Up @@ -262,8 +260,9 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
uint16_t *Size,
uint64_t Address, MCRegisterInfo *MRI)
{
uint32_t insn = 0;
DecodeStatus result;
uint32_t insn = 0;
DecodeStatus result;

if (code_len < 4) {
// not enough data
*Size = 0;
Expand Down Expand Up @@ -701,7 +700,7 @@ static DecodeStatus DecodeBitfieldInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address,
void *Decoder)
{
unsigned ExtractOp = 0, InsertOp = 0;
unsigned ExtractOp = 0, InsertOp = 0;
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
Expand Down Expand Up @@ -1167,7 +1166,7 @@ static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
// TransferBytes = NumVecs * OneLaneBytes
unsigned TransferBytes = 0;
unsigned NumVecs = 0;
unsigned Rt = 0, Rn = 0, Rm = 0, Q = 0, S = 0, lane = 0, NumLanes = 0;
unsigned Rt = 0, Rn = 0, Rm = 0, Q = 0, S = 0, lane = 0, NumLanes = 0;
unsigned Opc = MCInst_getOpcode(Inst);
switch (Opc) {
case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
Expand Down
10 changes: 5 additions & 5 deletions arch/AArch64/AArch64InstPrinter.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -315,8 +315,8 @@ static void printLabelOperand(MCInst *MI, unsigned OpNum,
SStream *O, unsigned field_width, unsigned scale)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
uint64_t UImm = 0, Sign = 0, SImm = 0;
int64_t tmp = 0;
uint64_t UImm = 0, Sign = 0, SImm = 0;
int64_t tmp = 0;
if (!MCOperand_isImm(MO)) {
printOperand(MI, OpNum, O);
return;
Expand Down Expand Up @@ -344,7 +344,7 @@ static void printLabelOperand(MCInst *MI, unsigned OpNum,
else
SStream_concat(O, "#%"PRIu64, SImm);
} else {
tmp = -(int64_t)SImm;
tmp = -(int64_t)SImm;
if (SImm < -HEX_THRESHOLD)
SStream_concat(O, "#-0x%"PRIx64, tmp);
else
Expand Down Expand Up @@ -398,7 +398,7 @@ static void printShiftOperand(MCInst *MI, unsigned OpNum,
SStream *O, A64SE_ShiftExtSpecifiers Shift)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
unsigned int imm = 0;
unsigned int imm = 0;
// LSL #0 is not printed
if (Shift == A64SE_LSL && MCOperand_isImm(MO) && MCOperand_getImm(MO) == 0)
return;
Expand Down Expand Up @@ -659,7 +659,7 @@ static void printNeonMovImmShiftOperand(MCInst *MI, unsigned OpNum,
SStream *O, A64SE_ShiftExtSpecifiers Ext, bool isHalf)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
int64_t Imm = 0;
int64_t Imm = 0;
//assert(MO.isImm() &&
// "Immediate operand required for Neon vector immediate inst.");

Expand Down
8 changes: 4 additions & 4 deletions arch/ARM/ARMAddressingModes.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,7 @@ static inline unsigned getSOImmValRot(unsigned Imm)
/// take a maximal chunk of bits out of the immediate.
static inline unsigned getSOImmValRotate(unsigned Imm)
{
unsigned TZ = 0, RotAmt = 0;
unsigned TZ = 0, RotAmt = 0;
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Imm & ~255U) == 0) return 0;
Expand Down Expand Up @@ -184,7 +184,7 @@ static inline unsigned getSOImmValRotate(unsigned Imm)
/// it. If not, return -1.
static inline int getSOImmVal(unsigned Arg)
{
unsigned RotAmt = 0;
unsigned RotAmt = 0;
// 8-bit (or less) immediates are trivially shifter_operands with a rotate
// of zero.
if ((Arg & ~255U) == 0) return Arg;
Expand Down Expand Up @@ -339,7 +339,7 @@ static inline int getT2SOImmValRotateVal(unsigned V)
/// See ARM Reference Manual A6.3.2.
static inline int getT2SOImmVal(unsigned Arg)
{
int Rot = 0;
int Rot = 0;
// If 'Arg' is an 8-bit splat, then get the encoded value.
int Splat = getT2SOImmValSplatVal(Arg);
if (Splat != -1)
Expand All @@ -355,7 +355,7 @@ static inline int getT2SOImmVal(unsigned Arg)

static inline unsigned getT2SOImmValRotate(unsigned V)
{
unsigned RotAmt = 0;
unsigned RotAmt = 0;
if ((V & ~255U) == 0) return 0;
// Use CTZ to compute the rotate amount.
RotAmt = CountTrailingZeros_32(V);
Expand Down
Loading

0 comments on commit 42706a3

Please sign in to comment.