project 1 code

project1/project_1_teamLoOsE_V0/code/ALU.v

@@ -0,0 +1,76 @@
+module ALU
+(
+	data1_i,
+	data2_i,
+	ALUCtrl_i,
+	data_o,
+	Zero_o
+);
+	// Port 
+	input [31:0] data1_i;
+	input [31:0] data2_i;
+	input [2:0] ALUCtrl_i;
+	output [31:0] data_o;
+	output Zero_o;
+
+	// Type
+	reg Zero_o;
+	reg [31:0] data_o;
+
+	localparam
+		ADD = 3'b010,
+		SUB = 3'b110,
+		OR = 3'b001,
+		AND = 3'b000,
+		MUL = 3'b111;
+
+	// Behavior block
+	always @(data1_i or data2_i or ALUCtrl_i) 
+		begin
+		case (ALUCtrl_i)
+			// add
+			ADD:
+				begin
+					Zero_o <= 0;
+					data_o <= data1_i + data2_i;
+				end
+			// substract
+			SUB:
+				begin
+					if (data1_i == data2_i)
+						Zero_o <= 1;
+					else
+						Zero_o <= 0;
+
+					data_o <= data1_i - data2_i; 
+				end
+			// and
+			AND:
+				begin
+					Zero_o <= 0;
+					data_o <= data1_i & data2_i;
+				end
+			// or
+			OR:
+				begin
+					Zero_o <= 0;
+					data_o <= data1_i | data2_i;
+				end
+			// mul 
+			MUL:
+				begin
+					Zero_o <= 0;
+					data_o <= data1_i * data2_i;
+				end
+			default: 
+				begin 
+					Zero_o <= 0;
+					data_o <= 0;
+				end
+			endcase
+		end
+
+
+
+
+endmodule

project1/project_1_teamLoOsE_V0/code/ALU_Control.v

@@ -0,0 +1,65 @@
+module ALU_Control(funct_i, ALUOp_i, ALUCtrl_o);
+	input [5:0] funct_i;
+	input [1:0] ALUOp_i;
+	output [2:0] ALUCtrl_o;
+
+	reg [2:0] ALUCtrl_o;
+
+	localparam
+		// ALUop
+		ALU_R_TYPE = 2'b11,
+		ALU_ADD = 2'b00,
+		ALU_SUB = 2'b01,
+		ALU_OR = 2'b10,
+		//
+		ADD = 3'b010,
+		SUB = 3'b110,
+		OR = 3'b001,
+		AND = 3'b000,
+		MUL = 3'b111;
+	always @(funct_i or ALUOp_i) begin
+		if (ALUOp_i == ALU_R_TYPE) begin
+			case (funct_i)
+			// add
+			6'b100000:
+				begin
+					ALUCtrl_o <= ADD;
+				end
+			// subtract
+			6'b100010:
+				begin
+					ALUCtrl_o <= SUB;
+				end
+			// and
+			6'b100100:
+				begin
+					ALUCtrl_o <= AND;
+				end
+			// or
+			6'b100101:
+				begin
+					ALUCtrl_o <= OR;
+				end
+			// mul
+			6'b011000:
+				begin
+					ALUCtrl_o <= MUL;
+				end
+			endcase
+		end
+
+		else if(ALUOp_i == ALU_ADD) begin
+			ALUCtrl_o <=  ADD; // addi will go into this 
+		end
+		else if(ALUOp_i == ALU_SUB) begin
+			ALUCtrl_o <= SUB;			
+		end
+		else if(ALUOp_i == ALU_OR) begin
+			ALUCtrl_o <= OR;		
+		end
+		else begin
+			// defualt ADD
+			ALUCtrl_o <= ADD;
+		end
+	end
+endmodule

project1/project_1_teamLoOsE_V0/code/ALU_add_only.v

@@ -0,0 +1,5 @@
+module ALU_add_only (inA, inB, add_out);
+	input [31:0] inA, inB;
+	output [31:0] add_out;
+	assign add_out=inA+inB;
+endmodule

project1/project_1_teamLoOsE_V0/code/Adder.v

@@ -0,0 +1,13 @@
+module Adder
+(
+	data1_in,
+	data2_in,
+	data_o
+);
+
+input [31:0] data1_in, data2_in;
+output [31:0] data_o;
+
+assign data_o = data1_in + data2_in;
+
+endmodule