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xillybus.txt: standardize document format
Each text file under Documentation follows a different format. Some doesn't even have titles! Change its representation to follow the adopted standard, using ReST markups for it to be parseable by Sphinx: - Adjust indentation; - Mark authorship; - Comment internal contents table; - Mark literal blocks; - Don't use all-upercase titles. Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Jonathan Corbet <[email protected]>
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Original file line number | Diff line number | Diff line change |
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@@ -1,12 +1,11 @@ | ||
========================================== | ||
Xillybus driver for generic FPGA interface | ||
========================================== | ||
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========================================== | ||
Xillybus driver for generic FPGA interface | ||
========================================== | ||
:Author: Eli Billauer, Xillybus Ltd. (http://xillybus.com) | ||
:Email: [email protected] or as advertised on Xillybus' site. | ||
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Author: Eli Billauer, Xillybus Ltd. (http://xillybus.com) | ||
Email: [email protected] or as advertised on Xillybus' site. | ||
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Contents: | ||
.. Contents: | ||
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- Introduction | ||
-- Background | ||
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@@ -17,7 +16,7 @@ Contents: | |
-- Synchronization | ||
-- Seekable pipes | ||
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- Internals | ||
- Internals | ||
-- Source code organization | ||
-- Pipe attributes | ||
-- Host never reads from the FPGA | ||
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@@ -29,7 +28,7 @@ Contents: | |
-- The "nonempty" message (supporting poll) | ||
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INTRODUCTION | ||
Introduction | ||
============ | ||
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Background | ||
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@@ -105,7 +104,7 @@ driver is used to work out of the box with any Xillybus IP core. | |
The data structure just mentioned should not be confused with PCI's | ||
configuration space or the Flattened Device Tree. | ||
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USAGE | ||
Usage | ||
===== | ||
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User interface | ||
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@@ -117,11 +116,11 @@ names of these files depend on the IP core that is loaded in the FPGA (see | |
Probing below). To communicate with the FPGA, open the device file that | ||
corresponds to the hardware FIFO you want to send data or receive data from, | ||
and use plain write() or read() calls, just like with a regular pipe. In | ||
particular, it makes perfect sense to go: | ||
particular, it makes perfect sense to go:: | ||
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$ cat mydata > /dev/xillybus_thisfifo | ||
$ cat mydata > /dev/xillybus_thisfifo | ||
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$ cat /dev/xillybus_thatfifo > hisdata | ||
$ cat /dev/xillybus_thatfifo > hisdata | ||
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possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have | ||
the capability to send an EOF (but may not use it). | ||
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@@ -178,7 +177,7 @@ the attached memory is done by seeking to the desired address, and calling | |
read() or write() as required. | ||
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INTERNALS | ||
Internals | ||
========= | ||
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Source code organization | ||
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@@ -365,7 +364,7 @@ into that page. It can be shown that all pages requested from the kernel | |
(except possibly for the last) are 100% utilized this way. | ||
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The "nonempty" message (supporting poll) | ||
--------------------------------------- | ||
---------------------------------------- | ||
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In order to support the "poll" method (and hence select() ), there is a small | ||
catch regarding the FPGA to host direction: The FPGA may have filled a DMA | ||
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