Tags: jjescof/linux-sunxi
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sunxi: Calculate PLL5P clock divisors for G2D, ACE and DEBE
When PLL5P is used as a parent clock for some of the peripherals,
the current code just selects some hardcoded divisors. This happens
to work, but only under assumption that the PLL5P clock speed is
somewhere between 360MHz and 480MHz (the typical DRAM clock speeds).
However with some tweaks for the DRAM parameters, it is possible to
clock DRAM up to 600MHz and more on some devices:
http://lists.denx.de/pipermail/u-boot/2014-July/183981.html
And this introduces concerns about the hardcoded divisors in the
kernel, which may cause some peripherals to operate at abnormally
high clock speeds if the PLL5 clock speed is too fast (PLL5 is used
for clocking DRAM).
Moreover, it makes sense to avoid pre-dividing PLL5P and make it run
even faster than DRAM. This provides better granularity of the clock
speed selection for MBUS, G2D and everything else that is using PLL5P
as the parent clock. but running PLL5P faster means that the hardcoded
divisors become even more inappropriate.
This patch improves the clock divisors selection for G2D, ACE and
DEBE to insure that they can work correctly with any PLL5P clock
speed.
Signed-off-by: Siarhei Siamashka <[email protected]>
Acked-by: Hans de Goede <[email protected]>
3.4.102 + minor fixes + latest android-3.4 changes
Merge branch 'reference-3.14' into experimental/sunxi-3.14
Merge branch 'reference-3.14' into experimental/sunxi-3.14
arm:configs: enable modules in sunxi_defconfig Signed-off-by: Alejandro Mery <[email protected]>
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