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drivers: clk: st: Remove stih415-416 clock support
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STiH415 and STiH416 platforms are no longer used.
these platforms will be deprecated for the next kernel.

Signed-off-by: Gabriel Fernandez <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Peter Griffin <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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@Gabriel-Fernandez-stm @bebarino
Gabriel-Fernandez-stm authored and bebarino committed Sep 16, 2016
1 parent f5644f1 commit 7df404c
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Showing 10 changed files with 37 additions and 1,639 deletions.
49 changes: 0 additions & 49 deletions Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
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18 changes: 7 additions & 11 deletions Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -10,13 +10,6 @@ This binding uses the common clock binding[1].
Required properties:

- compatible : shall be:
"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
"st,stih407-clkgen-a9-mux", "st,clkgen-mux"

- #clock-cells : from common clock binding; shall be set to 0.
Expand All @@ -27,10 +20,13 @@ Required properties:

Example:

clk_m_hva: clk-m-hva@fd690868 {
clk_m_a9: clk-m-a9@92b0000 {
#clock-cells = <0>;
compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
reg = <0xfd690868 4>;
compatible = "st,stih407-clkgen-a9-mux";
reg = <0x92b0000 0x10000>;

clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
clocks = <&clockgen_a9_pll 0>,
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};
26 changes: 6 additions & 20 deletions Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -9,25 +9,12 @@ Base address is located to the parent node. See clock binding[2]
Required properties:

- compatible : shall be:
"st,clkgena-prediv-c65", "st,clkgena-prediv"
"st,clkgena-prediv-c32", "st,clkgena-prediv"

"st,clkgena-plls-c65"
"st,plls-c32-a1x-0", "st,clkgen-plls-c32"
"st,plls-c32-a1x-1", "st,clkgen-plls-c32"
"st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih418-plls-c28-a9", "st,clkgen-plls-c32"

"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"

- #clock-cells : From common clock binding; shall be set to 1.

- clocks : From common clock binding
Expand All @@ -36,17 +23,16 @@ Required properties:

Example:

clockgen-a@fee62000 {
reg = <0xfee62000 0xb48>;
clockgen-a9@92b0000 {
compatible = "st,clkgen-c32";
reg = <0x92b0000 0xffff>;

clk_s_a0_pll: clk-s-a0-pll {
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";
compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";

clocks = <&clk_sysin>;

clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
clock-output-names = "clockgen-a9-pll-odf";
};
};
36 changes: 0 additions & 36 deletions Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
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61 changes: 0 additions & 61 deletions Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
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54 changes: 11 additions & 43 deletions Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -13,14 +13,6 @@ address is common of all subnode.
...
};

prediv_node {
...
};

divmux_node {
...
};

quadfs_node {
...
};
Expand All @@ -29,10 +21,6 @@ address is common of all subnode.
...
};

vcc_node {
...
};

flexgen_node {
...
};
Expand All @@ -43,11 +31,8 @@ This binding uses the common clock binding[1].
Each subnode should use the binding described in [2]..[7]

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
[6] Documentation/devicetree/bindings/clock/st,vcc.txt
[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
[8] Documentation/devicetree/bindings/clock/st,flexgen.txt

Expand All @@ -57,44 +42,27 @@ Required properties:

Example:

clockgen-a@fee62000 {

reg = <0xfee62000 0xb48>;
clockgen-a@090ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;

clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
compatible = "st,clkgena-plls-c65";

clocks = <&clk-sysin>;

clock-output-names = "clk-s-a0-pll0-hs",
"clk-s-a0-pll0-ls",
"clk-s-a0-pll1";
};

clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
#clock-cells = <0>;
compatible = "st,clkgena-prediv-c65",
"st,clkgena-prediv";
compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";

clocks = <&clk_sysin>;

clock-output-names = "clk-s-a0-osc-prediv";
clock-output-names = "clk-s-a0-pll-ofd-0";
};

clk_s_a0_hs: clk-s-a0-hs {
clk_s_a0_flexgen: clk-s-a0-flexgen {
compatible = "st,flexgen";

#clock-cells = <1>;
compatible = "st,clkgena-divmux-c65-hs",
"st,clkgena-divmux";

clocks = <&clk-s_a0_osc_prediv>,
<&clk-s_a0_pll 0>, /* pll0 hs */
<&clk-s_a0_pll 2>; /* pll1 */
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;

clock-output-names = "clk-s-fdma-0",
"clk-s-fdma-1",
""; /* clk-s-jit-sense */
/* fourth output unused */
clock-output-names = "clk-ic-lmi0";
};
};

27 changes: 12 additions & 15 deletions Documentation/devicetree/bindings/clock/st/st,quadfs.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -11,10 +11,6 @@ This binding uses the common clock binding[1].

Required properties:
- compatible : shall be:
"st,stih416-quadfs216", "st,quadfs"
"st,stih416-quadfs432", "st,quadfs"
"st,stih416-quadfs660-E", "st,quadfs"
"st,stih416-quadfs660-F", "st,quadfs"
"st,stih407-quadfs660-C", "st,quadfs"
"st,stih407-quadfs660-D", "st,quadfs"

Expand All @@ -35,14 +31,15 @@ Required properties:

Example:

clockgen_e: clockgen-e@fd3208bc {
#clock-cells = <1>;
compatible = "st,stih416-quadfs660-E", "st,quadfs";
reg = <0xfd3208bc 0xB0>;

clocks = <&clk_sysin>;
clock-output-names = "clk-m-pix-mdtp-0",
"clk-m-pix-mdtp-1",
"clk-m-pix-mdtp-2",
"clk-m-mpelpc";
};
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
#clock-cells = <1>;
compatible = "st,stih407-quadfs660-C", "st,quadfs";
reg = <0x9103000 0x1000>;

clocks = <&clk_sysin>;

clock-output-names = "clk-s-c0-fs0-ch0",
"clk-s-c0-fs0-ch1",
"clk-s-c0-fs0-ch2",
"clk-s-c0-fs0-ch3";
};
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