intel_adsp: Fix data cache flush before D3

Fix sys_cache_data_flush_range() calls during D3 entrance. Signed-off-by: Jaroslaw Stelter <[email protected]> Signed-off-by: Anas Nashif <[email protected]>
jmyllyla · Jun 12, 2024 · 6070e69 · 6070e69
1 parent a1ee7f9
commit 6070e69
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c
@@ -306,7 +306,7 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 			imr_layout->imr_state.header.imr_restore_vector =
 					(void *)boot_entry_d3_restore;
 			imr_layout->imr_state.header.imr_ram_storage = global_imr_ram_storage;
-			sys_cache_data_flush_range(imr_layout, sizeof(*imr_layout));
+			sys_cache_data_flush_range((void *)imr_layout, sizeof(*imr_layout));
 
 			/* save CPU context here
 			 * when _restore_core_context() is called, it will return directly to
@@ -337,7 +337,7 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 #else
 			imr_layout->imr_state.header.imr_restore_vector =
 					(void *)rom_entry;
-			sys_cache_data_flush_range(imr_layout, sizeof(*imr_layout));
+			sys_cache_data_flush_range((void *)imr_layout, sizeof(*imr_layout));
 #endif /* CONFIG_ADSP_IMR_CONTEXT_SAVE */
 			uint32_t hpsram_mask = 0;
 #ifdef CONFIG_ADSP_POWER_DOWN_HPSRAM