soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS)

This commit adds support for the Broadcom STB S2/S3/S5 suspend states on MIPS based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY - DDR memory controller and arbiter - control processor The final steps of the suspend execute in cache and there is is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wait loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. Signed-off-by: Justin Chen <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
josf · Sep 25, 2017 · 0e9b114 · 0e9b114
1 parent dedcf23
commit 0e9b114
Show file tree

Hide file tree

Showing 6 changed files with 821 additions and 2 deletions.
diff --git a/drivers/soc/bcm/brcmstb/Kconfig b/drivers/soc/bcm/brcmstb/Kconfig
@@ -4,7 +4,7 @@ config BRCMSTB_PM
 	bool "Support suspend/resume for STB platforms"
 	default y
 	depends on PM
-	depends on ARCH_BRCMSTB
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
 	select ARM_CPU_SUSPEND if ARM
 
 endif # SOC_BRCMSTB
diff --git a/drivers/soc/bcm/brcmstb/pm/Makefile b/drivers/soc/bcm/brcmstb/pm/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_ARM)		+= s2-arm.o pm-arm.o
 AFLAGS_s2-arm.o			:= -march=armv7-a
+obj-$(CONFIG_BMIPS_GENERIC)	+= s2-mips.o s3-mips.o pm-mips.o