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Merge tag 'mips_5.19' of git://git.kernel.org/pub/scm/linux/kernel/gi…
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…t/mips/linux

Pull MIPS updates from Thomas Bogendoerfer:
 "Cleanups and fixes"

* tag 'mips_5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (38 commits)
  MIPS: RALINK: Define pci_remap_iospace under CONFIG_PCI_DRIVERS_GENERIC
  MIPS: Use memblock_add_node() in early_parse_mem() under CONFIG_NUMA
  MIPS: Return -EINVAL if mem parameter is empty in early_parse_mem()
  MIPS: Kconfig: Fix indentation and add endif comment
  MIPS: bmips: Fix compiler warning observed on W=1 build
  MIPS: Rewrite `csum_tcpudp_nofold' in plain C
  mips: setup: use strscpy to replace strlcpy
  MIPS: Octeon: add SNIC10E board
  MIPS: Ingenic: Refresh defconfig for CU1000-Neo and CU1830-Neo.
  MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.
  MIPS: Ingenic: Add PWM nodes for X1830.
  MIPS: Octeon: fix typo in comment
  MIPS: loongson32: Kconfig: Remove extra space
  MIPS: Sibyte: remove unnecessary return variable
  MIPS: Use NOKPROBE_SYMBOL() instead of __kprobes annotation
  selftests/ftrace: Save kprobe_events to test log
  MIPS: tools: no need to initialise statics to 0
  MIPS: Loongson: Use hwmon_device_register_with_groups() to register hwmon
  MIPS: VR41xx: Drop redundant spinlock initialization
  MIPS: smp: optimization for flush_tlb_mm when exiting
  ...
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@torvalds
torvalds committed May 30, 2022
2 parents 2d2da47 + 7e4fd16 commit 73d15ba
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Showing 62 changed files with 401 additions and 335 deletions.
12 changes: 6 additions & 6 deletions arch/mips/Kconfig
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Expand Up @@ -1321,11 +1321,11 @@ config CPU_LOONGSON64
select SWIOTLB
select HAVE_KVM
help
The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
cores implements the MIPS64R2 instruction set with many extensions,
including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
Loongson-2E/2F is not covered here and will be removed in future.
The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
cores implements the MIPS64R2 instruction set with many extensions,
including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
Loongson-2E/2F is not covered here and will be removed in future.

config LOONGSON3_ENHANCEMENT
bool "New Loongson-3 CPU Enhancements"
Expand Down Expand Up @@ -3255,7 +3255,7 @@ menu "CPU Power Management"

if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
source "drivers/cpufreq/Kconfig"
endif
endif # CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER

source "drivers/cpuidle/Kconfig"

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2 changes: 1 addition & 1 deletion arch/mips/alchemy/common/dbdma.c
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Expand Up @@ -574,7 +574,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
dp++;
}

/* Make last descrptor point to the first. */
/* Make last descriptor point to the first. */
dp--;
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
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1 change: 1 addition & 0 deletions arch/mips/bmips/dma.c
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@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+

#include <linux/types.h>
#include <linux/dma-map-ops.h>
#include <asm/bmips.h>
#include <asm/io.h>

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2 changes: 1 addition & 1 deletion arch/mips/boot/dts/brcm/bcm97358svmb.dts
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Expand Up @@ -78,7 +78,7 @@
&qspi {
status = "okay";

m25p80@0 {
flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
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2 changes: 1 addition & 1 deletion arch/mips/boot/dts/brcm/bcm97360svmb.dts
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Expand Up @@ -81,7 +81,7 @@
&qspi {
status = "okay";

m25p80@0 {
flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
Expand Down
2 changes: 1 addition & 1 deletion arch/mips/boot/dts/brcm/bcm97425svmb.dts
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Expand Up @@ -116,7 +116,7 @@
&qspi {
status = "okay";

m25p80@0 {
flash@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
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77 changes: 40 additions & 37 deletions arch/mips/boot/dts/ingenic/cu1000-neo.dts
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Expand Up @@ -31,42 +31,6 @@
};
};

ssi: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <1>;

mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;

status = "okay";

spi-max-frequency = <50000000>;

sc16is752: expander@0 {
compatible = "nxp,sc16is752";
reg = <0>; /* CE0 */
spi-max-frequency = <4000000>;

clocks = <&exclk_sc16is752>;

interrupt-parent = <&gpc>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;

gpio-controller;
#gpio-cells = <2>;

exclk_sc16is752: sc16is752 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
};

wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";

Expand All @@ -90,7 +54,7 @@

&ost {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};

Expand All @@ -101,6 +65,39 @@
pinctrl-0 = <&pins_uart2>;
};

&ssi {
status = "okay";

num-cs = <2>;
cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;

pinctrl-names = "default";
pinctrl-0 = <&pins_ssi>;

sc16is752: expander@0 {
compatible = "nxp,sc16is752";
reg = <0>; /* CE0 */

spi-rx-bus-width = <1>;
spi-tx-bus-width = <1>;
spi-max-frequency = <4000000>;

clocks = <&exclk_sc16is752>;

interrupt-parent = <&gpc>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;

gpio-controller;
#gpio-cells = <2>;

exclk_sc16is752: sc16is752 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
};

&i2c0 {
status = "okay";

Expand Down Expand Up @@ -192,6 +189,12 @@
bias-pull-up;
};

pins_ssi: ssi {
function = "ssi";
groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
bias-disable;
};

pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
Expand Down
76 changes: 39 additions & 37 deletions arch/mips/boot/dts/ingenic/cu1830-neo.dts
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Expand Up @@ -31,42 +31,6 @@
};
};

ssi0: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <1>;

mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;

status = "okay";

spi-max-frequency = <50000000>;

sc16is752: expander@0 {
compatible = "nxp,sc16is752";
reg = <0>; /* CE0 */
spi-max-frequency = <4000000>;

clocks = <&exclk_sc16is752>;

interrupt-parent = <&gpb>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;

gpio-controller;
#gpio-cells = <2>;

exclk_sc16is752: sc16is752 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
};

wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";

Expand All @@ -90,7 +54,7 @@

&ost {
/* 1500 kHz for the system timer and clocksource */
assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};

Expand All @@ -101,6 +65,38 @@
pinctrl-0 = <&pins_uart1>;
};

&ssi0 {
status = "okay";

num-cs = <2>;

pinctrl-names = "default";
pinctrl-0 = <&pins_ssi0>;

sc16is752: expander@0 {
compatible = "nxp,sc16is752";
reg = <0>; /* CE0 */

spi-rx-bus-width = <1>;
spi-tx-bus-width = <1>;
spi-max-frequency = <4000000>;

clocks = <&exclk_sc16is752>;

interrupt-parent = <&gpb>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;

gpio-controller;
#gpio-cells = <2>;

exclk_sc16is752: sc16is752 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
};

&i2c0 {
status = "okay";

Expand Down Expand Up @@ -196,6 +192,12 @@
bias-pull-up;
};

pins_ssi0: ssi0 {
function = "ssi0";
groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
bias-disable;
};

pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
Expand Down
32 changes: 32 additions & 0 deletions arch/mips/boot/dts/ingenic/x1000.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,18 @@
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};

pwm: pwm@40 {
compatible = "ingenic,x1000-pwm";
reg = <0x40 0x50>;

#pwm-cells = <3>;

clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
<&tcu TCU_CLK_TIMER4>;
clock-names = "timer0", "timer1", "timer2", "timer3", "timer4";
};
};

rtc: rtc@10003000 {
Expand Down Expand Up @@ -246,6 +258,25 @@
status = "disabled";
};

ssi: spi@10043000 {
compatible = "ingenic,x1000-spi";
reg = <0x10043000 0x20>;
#address-cells = <1>;
#size-cells = <0>;

interrupt-parent = <&intc>;
interrupts = <8>;

clocks = <&cgu X1000_CLK_SSI>;
clock-names = "spi";

dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
<&pdma X1000_DMA_SSI0_TX 0xffffffff>;
dma-names = "rx", "tx";

status = "disabled";
};

i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
Expand Down Expand Up @@ -291,6 +322,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1000-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;

#dma-cells = <2>;

interrupt-parent = <&intc>;
Expand Down
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