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Merge tag 'usb-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big USB and PHY driver updates for 4.11-rc1. Nothing major, just the normal amount of churn in the usb gadget and dwc and xhci controllers, new device ids, new phy drivers, a new usb-serial driver, and a few other minor changes in different USB drivers. All have been in linux-next for a long time with no reported issues" * tag 'usb-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (265 commits) usb: cdc-wdm: remove logically dead code USB: serial: keyspan: drop header file USB: serial: io_edgeport: drop io-tables header file usb: musb: add code comment for clarification usb: misc: add USB251xB/xBi Hi-Speed Hub Controller Driver usb: misc: usbtest: remove redundant check on retval < 0 USB: serial: upd78f0730: sort device ids USB: serial: upd78f0730: add ID for EVAL-ADXL362Z ohci-hub: fix typo in dbg_port macro usb: musb: dsps: Manage CPPI 4.1 DMA interrupt in DSPS usb: musb: tusb6010: Clean up tusb_omap_dma structure usb: musb: cppi_dma: Clean up cppi41_dma_controller structure usb: musb: cppi_dma: Clean up cppi structure usb: musb: cppi41: Detect aborted transfers in cppi41_dma_callback() usb: musb: dma: Add a DMA completion platform callback drivers: usb: usbip: Add missing break statement to switch usb: mtu3: remove redundant dev_err call in get_ssusb_rscs() USB: serial: mos7840: fix another NULL-deref at open USB: serial: console: clean up sanity checks USB: serial: console: fix uninitialised spinlock ...
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Documentation/devicetree/bindings/phy/brcm,nsp-usb3-phy.txt
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| Broadcom USB3 phy binding for northstar plus SoC | ||
| The USB3 phy is internal to the SoC and is accessed using mdio interface. | ||
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| Required mdio bus properties: | ||
| - reg: Should be 0x0 for SoC internal USB3 phy | ||
| - #address-cells: must be 1 | ||
| - #size-cells: must be 0 | ||
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| Required USB3 PHY properties: | ||
| - compatible: should be "brcm,nsp-usb3-phy" | ||
| - reg: USB3 Phy address on SoC internal MDIO bus and it should be 0x10. | ||
| - usb3-ctrl-syscon: handler of syscon node defining physical address | ||
| of usb3 control register. | ||
| - #phy-cells: must be 0 | ||
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| Required usb3 control properties: | ||
| - compatible: should be "brcm,nsp-usb3-ctrl" | ||
| - reg: offset and length of the control registers | ||
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| Example: | ||
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| mdio@0 { | ||
| reg = <0x0>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| usb3_phy: usb-phy@10 { | ||
| compatible = "brcm,nsp-usb3-phy"; | ||
| reg = <0x10>; | ||
| usb3-ctrl-syscon = <&usb3_ctrl>; | ||
| #phy-cells = <0>; | ||
| status = "disabled"; | ||
| }; | ||
| }; | ||
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| usb3_ctrl: syscon@104408 { | ||
| compatible = "brcm,nsp-usb3-ctrl", "syscon"; | ||
| reg = <0x104408 0x3fc>; | ||
| }; |
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| Qualcomm's USB HS PHY | ||
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| PROPERTIES | ||
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| - compatible: | ||
| Usage: required | ||
| Value type: <string> | ||
| Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the | ||
| following: | ||
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| "qcom,usb-hs-phy-apq8064" | ||
| "qcom,usb-hs-phy-msm8916" | ||
| "qcom,usb-hs-phy-msm8974" | ||
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| - #phy-cells: | ||
| Usage: required | ||
| Value type: <u32> | ||
| Definition: Should contain 0 | ||
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| - clocks: | ||
| Usage: required | ||
| Value type: <prop-encoded-array> | ||
| Definition: Should contain clock specifier for the reference and sleep | ||
| clocks | ||
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| - clock-names: | ||
| Usage: required | ||
| Value type: <stringlist> | ||
| Definition: Should contain "ref" and "sleep" for the reference and sleep | ||
| clocks respectively | ||
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| - resets: | ||
| Usage: required | ||
| Value type: <prop-encoded-array> | ||
| Definition: Should contain the phy and POR resets | ||
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| - reset-names: | ||
| Usage: required | ||
| Value type: <stringlist> | ||
| Definition: Should contain "phy" and "por" for the phy and POR resets | ||
| respectively | ||
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| - v3p3-supply: | ||
| Usage: required | ||
| Value type: <phandle> | ||
| Definition: Should contain a reference to the 3.3V supply | ||
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| - v1p8-supply: | ||
| Usage: required | ||
| Value type: <phandle> | ||
| Definition: Should contain a reference to the 1.8V supply | ||
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| - extcon: | ||
| Usage: optional | ||
| Value type: <prop-encoded-array> | ||
| Definition: Should contain the vbus extcon | ||
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| - qcom,init-seq: | ||
| Usage: optional | ||
| Value type: <u8 array> | ||
| Definition: Should contain a sequence of ULPI address and value pairs to | ||
| program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related | ||
| to Device Mode Eye Diagram test. The addresses are offsets | ||
| from the ULPI_EXT_VENDOR_SPECIFIC address, for example, | ||
| <0x1 0x53> would mean "write the value 0x53 to address 0x81". | ||
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| EXAMPLE | ||
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| otg: usb-controller { | ||
| ulpi { | ||
| phy { | ||
| compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; | ||
| #phy-cells = <0>; | ||
| clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; | ||
| clock-names = "ref", "sleep"; | ||
| resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; | ||
| reset-names = "phy", "por"; | ||
| v3p3-supply = <&pm8941_l24>; | ||
| v1p8-supply = <&pm8941_l6>; | ||
| extcon = <&smbb>; | ||
| qcom,init-seq = /bits/ 8 <0x1 0x63>; | ||
| }; | ||
| }; | ||
| }; |
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65
Documentation/devicetree/bindings/phy/qcom,usb-hsic-phy.txt
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| Original file line number | Diff line number | Diff line change |
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| Qualcomm's USB HSIC PHY | ||
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| PROPERTIES | ||
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| - compatible: | ||
| Usage: required | ||
| Value type: <string> | ||
| Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the | ||
| following: | ||
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| "qcom,usb-hsic-phy-mdm9615" | ||
| "qcom,usb-hsic-phy-msm8974" | ||
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| - #phy-cells: | ||
| Usage: required | ||
| Value type: <u32> | ||
| Definition: Should contain 0 | ||
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| - clocks: | ||
| Usage: required | ||
| Value type: <prop-encoded-array> | ||
| Definition: Should contain clock specifier for phy, calibration and | ||
| a calibration sleep clock | ||
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| - clock-names: | ||
| Usage: required | ||
| Value type: <stringlist> | ||
| Definition: Should contain "phy, "cal" and "cal_sleep" | ||
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| - pinctrl-names: | ||
| Usage: required | ||
| Value type: <stringlist> | ||
| Definition: Should contain "init" and "default" in that order | ||
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| - pinctrl-0: | ||
| Usage: required | ||
| Value type: <prop-encoded-array> | ||
| Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch | ||
| free state | ||
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| - pinctrl-1: | ||
| Usage: required | ||
| Value type: <prop-encoded-array> | ||
| Definition: List of pinctrl settings to apply to mux out the HSIC pins | ||
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| EXAMPLE | ||
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| usb-controller { | ||
| ulpi { | ||
| phy { | ||
| compatible = "qcom,usb-hsic-phy-msm8974", | ||
| "qcom,usb-hsic-phy"; | ||
| #phy-cells = <0>; | ||
| pinctrl-names = "init", "default"; | ||
| pinctrl-0 = <&hsic_sleep>; | ||
| pinctrl-1 = <&hsic_default>; | ||
| clocks = <&gcc GCC_USB_HSIC_CLK>, | ||
| <&gcc GCC_USB_HSIC_IO_CAL_CLK>, | ||
| <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>; | ||
| clock-names = "phy", "cal", "cal_sleep"; | ||
| assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>; | ||
| assigned-clock-rates = <960000>; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,20 @@ | ||
| ULPI bus binding | ||
| ---------------- | ||
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| Phys that are behind a ULPI connection can be described with the following | ||
| binding. The host controller shall have a "ulpi" named node as a child, and | ||
| that node shall have one enabled node underneath it representing the ulpi | ||
| device on the bus. | ||
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| EXAMPLE | ||
| ------- | ||
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| usb { | ||
| compatible = "vendor,usb-controller"; | ||
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| ulpi { | ||
| phy { | ||
| compatible = "vendor,phy"; | ||
| }; | ||
| }; | ||
| }; |
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