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Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/ker…
…nel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.14 kernel. Not so
much going on. No core changes, just drivers.
The most interesting would be that MIPS Ralink is migrating to pin
control and we have some bindings but not yet code for the Apple M1
pin controller.
New drivers:
- Last merge window we created a driver for the Ralink RT2880. We are
now moving the Ralink SoC pin control drivers out of the MIPS
architecture code and into the pin control subsystem. This concerns
RT288X, MT7620, RT305X, RT3883 and MT7621.
- Qualcomm SM6125 SoC pin control driver.
- Qualcomm spmi-gpio support for PM7325.
- Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)
- Mediatek MT8365 SoC pin controller.
- New device HID for the AMD GPIO controller.
Improvements:
- Pin bias config support for a slew of Renesas pin controllers.
- Incremental improvements and non-urgent bug fixes to the Renesas
SoC drivers.
- Implement irq_set_wake on the AMD pin controller so we can wake up
from external pin events.
Misc:
- Devicetree bindings for the Apple M1 pin controller, we will
probably see a proper driver for this soon as well"
* tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits)
pinctrl: ralink: rt305x: add missing include
pinctrl: stm32: check for IRQ MUX validity during alloc()
pinctrl: zynqmp: some code cleanups
drivers: qcom: pinctrl: Add pinctrl driver for sm6125
dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver
dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios
pinctrl: mcp23s08: Add optional reset GPIO
pinctrl: mediatek: fix mode encoding
pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
pinctrl: bcm: Constify static pinmux_ops
pinctrl: bcm: Constify static pinctrl_ops
pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file
pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file
pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file
pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file
pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
pinctrl: ralink: move ralink architecture pinmux header into the driver
pinctrl: single: config: enable the pin's input
pinctrl: mtk: Fix mt8365 Kconfig dependency
pinctrl: mcp23s08: fix race condition in irq handler
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Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
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| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: Apple GPIO controller | ||
|
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||
| maintainers: | ||
| - Mark Kettenis <[email protected]> | ||
|
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||
| description: | | ||
| The Apple GPIO controller is a simple combined pin and GPIO | ||
| controller present on Apple ARM SoC platforms, including various | ||
| iPhone and iPad devices and the "Apple Silicon" Macs. | ||
| properties: | ||
| compatible: | ||
| items: | ||
| - const: apple,t8103-pinctrl | ||
| - const: apple,pinctrl | ||
|
|
||
| reg: | ||
| maxItems: 1 | ||
|
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| clocks: | ||
| maxItems: 1 | ||
|
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| gpio-controller: true | ||
|
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| '#gpio-cells': | ||
| const: 2 | ||
|
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| gpio-ranges: | ||
| maxItems: 1 | ||
|
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||
| interrupts: | ||
| description: One interrupt for each of the (up to 7) interrupt | ||
| groups supported by the controller sorted by interrupt group | ||
| number in ascending order. | ||
| minItems: 1 | ||
| maxItems: 7 | ||
|
|
||
| interrupt-controller: true | ||
|
|
||
| patternProperties: | ||
| '-pins$': | ||
| type: object | ||
| $ref: pinmux-node.yaml# | ||
|
|
||
| properties: | ||
| pinmux: | ||
| description: | ||
| Values are constructed from pin number and alternate function | ||
| configuration number using the APPLE_PINMUX() helper macro | ||
| defined in include/dt-bindings/pinctrl/apple.h. | ||
|
|
||
| required: | ||
| - pinmux | ||
|
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| additionalProperties: false | ||
|
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| required: | ||
| - compatible | ||
| - reg | ||
| - gpio-controller | ||
| - '#gpio-cells' | ||
| - gpio-ranges | ||
|
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| additionalProperties: false | ||
|
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||
| examples: | ||
| - | | ||
| #include <dt-bindings/interrupt-controller/apple-aic.h> | ||
| #include <dt-bindings/pinctrl/apple.h> | ||
| soc { | ||
| #address-cells = <2>; | ||
| #size-cells = <2>; | ||
| pinctrl: pinctrl@23c100000 { | ||
| compatible = "apple,t8103-pinctrl", "apple,pinctrl"; | ||
| reg = <0x2 0x3c100000 0x0 0x100000>; | ||
| clocks = <&gpio_clk>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| gpio-ranges = <&pinctrl 0 0 212>; | ||
| interrupt-controller; | ||
| interrupt-parent = <&aic>; | ||
| interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>, | ||
| <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>; | ||
| pcie_pins: pcie-pins { | ||
| pinmux = <APPLE_PINMUX(150, 1)>, | ||
| <APPLE_PINMUX(151, 1)>, | ||
| <APPLE_PINMUX(32, 1)>; | ||
| }; | ||
| }; | ||
| }; |
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55
Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt
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Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml
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| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
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| title: Broadcom Northstar pins mux controller | ||
|
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| maintainers: | ||
| - Rafał Miłecki <[email protected]> | ||
|
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| description: | ||
| Some of Northstar SoCs's pins can be used for various purposes thanks to the | ||
| mux controller. This binding allows describing mux controller and listing | ||
| available functions. They can be referenced later by other bindings to let | ||
| system configure controller correctly. | ||
|
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| A list of pins varies across chipsets so few bindings are available. | ||
|
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| Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" | ||
| node. | ||
|
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||
| properties: | ||
| compatible: | ||
| enum: | ||
| - brcm,bcm4708-pinmux | ||
| - brcm,bcm4709-pinmux | ||
| - brcm,bcm53012-pinmux | ||
|
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||
| offset: | ||
| description: offset of pin registers in the CRU block | ||
| maxItems: 1 | ||
| $ref: /schemas/types.yaml#/definitions/uint32-array | ||
|
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| patternProperties: | ||
| '-pins$': | ||
| type: object | ||
| description: pin node | ||
| $ref: pinmux-node.yaml# | ||
|
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| properties: | ||
| function: | ||
| enum: [ spi, i2c, pwm, uart1, mdio, uart2, sdio ] | ||
| groups: | ||
| minItems: 1 | ||
| maxItems: 4 | ||
| items: | ||
| enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, | ||
| uart1_grp, mdio_grp, uart2_grp, sdio_pwr_grp, sdio_1p8v_grp ] | ||
|
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| required: | ||
| - function | ||
| - groups | ||
|
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| additionalProperties: false | ||
|
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| allOf: | ||
| - if: | ||
| properties: | ||
| compatible: | ||
| contains: | ||
| const: brcm,bcm4708-pinmux | ||
| then: | ||
| patternProperties: | ||
| '-pins$': | ||
| properties: | ||
| function: | ||
| enum: [ spi, i2c, pwm, uart1 ] | ||
| groups: | ||
| items: | ||
| enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, | ||
| uart1_grp ] | ||
|
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| required: | ||
| - offset | ||
|
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| additionalProperties: false | ||
|
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| examples: | ||
| - | | ||
| cru@1800c100 { | ||
| compatible = "syscon", "simple-mfd"; | ||
| reg = <0x1800c100 0x1a4>; | ||
| pinctrl { | ||
| compatible = "brcm,bcm4708-pinmux"; | ||
| offset = <0xc0>; | ||
| spi-pins { | ||
| function = "spi"; | ||
| groups = "spi_grp"; | ||
| }; | ||
| }; | ||
| }; |
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