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Merge branch 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/gregkh/usb-2.6
* 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (205 commits)
USB: EHCI: Remove SPARC_LEON {read,write}_be definitions from ehci.h
USB: UHCI: Support big endian GRUSBHC HC
sparc: add {read,write}*_be routines
USB: UHCI: Add support for big endian descriptors
USB: UHCI: Use ACCESS_ONCE rather than using a full compiler barrier
USB: UHCI: Add support for big endian mmio
usb-storage: Correct adjust_quirks to include latest flags
usb/isp1760: Fix possible unlink problems
usb/isp1760: Move function isp1760_endpoint_disable() within file.
USB: remove remaining usages of hcd->state from usbcore and fix regression
usb: musb: ux500: add configuration and build options for ux500 dma
usb: musb: ux500: add dma glue layer for ux500
usb: musb: ux500: add dma name for ux500
usb: musb: ux500: add ux500 specific code for gadget side
usb: musb: fix compile error
usb-storage: fix up the unusual_realtek device list
USB: gadget: f_audio: Fix invalid dereference of initdata
EHCI: don't rescan interrupt QHs needlessly
OHCI: fix regression caused by nVidia shutdown workaround
USB: OTG: msm: Free VCCCX regulator even if we can't set the voltage
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -4253,7 +4253,7 @@ F: include/linux/isicom.h | |
| MUSB MULTIPOINT HIGH SPEED DUAL-ROLE CONTROLLER | ||
| M: Felipe Balbi <[email protected]> | ||
| L: [email protected] | ||
| T: git git://gitorious.org/usb/usb.git | ||
| T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git | ||
| S: Maintained | ||
| F: drivers/usb/musb/ | ||
|
|
||
|
|
@@ -4588,6 +4588,7 @@ M: Felipe Balbi <[email protected]> | |
| M: David Brownell <[email protected]> | ||
| L: [email protected] | ||
| L: [email protected] | ||
| T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git | ||
| S: Maintained | ||
| F: drivers/usb/*/*omap* | ||
| F: arch/arm/*omap*/usb* | ||
|
|
||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,64 @@ | ||
| /* | ||
| * Copyright (C) 2011 Samsung Electronics Co.Ltd | ||
| * Author: Joonyoung Shim <[email protected]> | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify it | ||
| * under the terms of the GNU General Public License as published by the | ||
| * Free Software Foundation; either version 2 of the License, or (at your | ||
| * option) any later version. | ||
| */ | ||
|
|
||
| #ifndef __PLAT_S5P_REGS_USB_PHY_H | ||
| #define __PLAT_S5P_REGS_USB_PHY_H | ||
|
|
||
| #define EXYNOS4_HSOTG_PHYREG(x) ((x) + S5P_VA_USB_HSPHY) | ||
|
|
||
| #define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00) | ||
| #define PHY1_HSIC_NORMAL_MASK (0xf << 9) | ||
| #define PHY1_HSIC1_SLEEP (1 << 12) | ||
| #define PHY1_HSIC1_FORCE_SUSPEND (1 << 11) | ||
| #define PHY1_HSIC0_SLEEP (1 << 10) | ||
| #define PHY1_HSIC0_FORCE_SUSPEND (1 << 9) | ||
|
|
||
| #define PHY1_STD_NORMAL_MASK (0x7 << 6) | ||
| #define PHY1_STD_SLEEP (1 << 8) | ||
| #define PHY1_STD_ANALOG_POWERDOWN (1 << 7) | ||
| #define PHY1_STD_FORCE_SUSPEND (1 << 6) | ||
|
|
||
| #define PHY0_NORMAL_MASK (0x39 << 0) | ||
| #define PHY0_SLEEP (1 << 5) | ||
| #define PHY0_OTG_DISABLE (1 << 4) | ||
| #define PHY0_ANALOG_POWERDOWN (1 << 3) | ||
| #define PHY0_FORCE_SUSPEND (1 << 0) | ||
|
|
||
| #define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04) | ||
| #define PHY1_COMMON_ON_N (1 << 7) | ||
| #define PHY0_COMMON_ON_N (1 << 4) | ||
| #define PHY0_ID_PULLUP (1 << 2) | ||
| #define CLKSEL_MASK (0x3 << 0) | ||
| #define CLKSEL_SHIFT (0) | ||
| #define CLKSEL_48M (0x0 << 0) | ||
| #define CLKSEL_12M (0x2 << 0) | ||
| #define CLKSEL_24M (0x3 << 0) | ||
|
|
||
| #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) | ||
| #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) | ||
| #define HOST_LINK_PORT2_SWRST (1 << 9) | ||
| #define HOST_LINK_PORT1_SWRST (1 << 8) | ||
| #define HOST_LINK_PORT0_SWRST (1 << 7) | ||
| #define HOST_LINK_ALL_SWRST (1 << 6) | ||
|
|
||
| #define PHY1_SWRST_MASK (0x7 << 3) | ||
| #define PHY1_HSIC_SWRST (1 << 5) | ||
| #define PHY1_STD_SWRST (1 << 4) | ||
| #define PHY1_ALL_SWRST (1 << 3) | ||
|
|
||
| #define PHY0_SWRST_MASK (0x7 << 0) | ||
| #define PHY0_PHYLINK_SWRST (1 << 2) | ||
| #define PHY0_HLINK_SWRST (1 << 1) | ||
| #define PHY0_SWRST (1 << 0) | ||
|
|
||
| #define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34) | ||
| #define FPENABLEN (1 << 0) | ||
|
|
||
| #endif /* __PLAT_S5P_REGS_USB_PHY_H */ |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,136 @@ | ||
| /* | ||
| * Copyright (C) 2011 Samsung Electronics Co.Ltd | ||
| * Author: Joonyoung Shim <[email protected]> | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify it | ||
| * under the terms of the GNU General Public License as published by the | ||
| * Free Software Foundation; either version 2 of the License, or (at your | ||
| * option) any later version. | ||
| * | ||
| */ | ||
|
|
||
| #include <linux/clk.h> | ||
| #include <linux/delay.h> | ||
| #include <linux/err.h> | ||
| #include <linux/io.h> | ||
| #include <linux/platform_device.h> | ||
| #include <mach/regs-pmu.h> | ||
| #include <mach/regs-usb-phy.h> | ||
| #include <plat/cpu.h> | ||
| #include <plat/usb-phy.h> | ||
|
|
||
| static int exynos4_usb_phy1_init(struct platform_device *pdev) | ||
| { | ||
| struct clk *otg_clk; | ||
| struct clk *xusbxti_clk; | ||
| u32 phyclk; | ||
| u32 rstcon; | ||
| int err; | ||
|
|
||
| otg_clk = clk_get(&pdev->dev, "otg"); | ||
| if (IS_ERR(otg_clk)) { | ||
| dev_err(&pdev->dev, "Failed to get otg clock\n"); | ||
| return PTR_ERR(otg_clk); | ||
| } | ||
|
|
||
| err = clk_enable(otg_clk); | ||
| if (err) { | ||
| clk_put(otg_clk); | ||
| return err; | ||
| } | ||
|
|
||
| writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE, | ||
| S5P_USBHOST_PHY_CONTROL); | ||
|
|
||
| /* set clock frequency for PLL */ | ||
| phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; | ||
|
|
||
| xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); | ||
| if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { | ||
| switch (clk_get_rate(xusbxti_clk)) { | ||
| case 12 * MHZ: | ||
| phyclk |= CLKSEL_12M; | ||
| break; | ||
| case 24 * MHZ: | ||
| phyclk |= CLKSEL_24M; | ||
| break; | ||
| default: | ||
| case 48 * MHZ: | ||
| /* default reference clock */ | ||
| break; | ||
| } | ||
| clk_put(xusbxti_clk); | ||
| } | ||
|
|
||
| writel(phyclk, EXYNOS4_PHYCLK); | ||
|
|
||
| /* floating prevention logic: disable */ | ||
| writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON); | ||
|
|
||
| /* set to normal HSIC 0 and 1 of PHY1 */ | ||
| writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK), | ||
| EXYNOS4_PHYPWR); | ||
|
|
||
| /* set to normal standard USB of PHY1 */ | ||
| writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR); | ||
|
|
||
| /* reset all ports of both PHY and Link */ | ||
| rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK | | ||
| PHY1_SWRST_MASK; | ||
| writel(rstcon, EXYNOS4_RSTCON); | ||
| udelay(10); | ||
|
|
||
| rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK); | ||
| writel(rstcon, EXYNOS4_RSTCON); | ||
| udelay(50); | ||
|
|
||
| clk_disable(otg_clk); | ||
| clk_put(otg_clk); | ||
|
|
||
| return 0; | ||
| } | ||
|
|
||
| static int exynos4_usb_phy1_exit(struct platform_device *pdev) | ||
| { | ||
| struct clk *otg_clk; | ||
| int err; | ||
|
|
||
| otg_clk = clk_get(&pdev->dev, "otg"); | ||
| if (IS_ERR(otg_clk)) { | ||
| dev_err(&pdev->dev, "Failed to get otg clock\n"); | ||
| return PTR_ERR(otg_clk); | ||
| } | ||
|
|
||
| err = clk_enable(otg_clk); | ||
| if (err) { | ||
| clk_put(otg_clk); | ||
| return err; | ||
| } | ||
|
|
||
| writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN), | ||
| EXYNOS4_PHYPWR); | ||
|
|
||
| writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE, | ||
| S5P_USBHOST_PHY_CONTROL); | ||
|
|
||
| clk_disable(otg_clk); | ||
| clk_put(otg_clk); | ||
|
|
||
| return 0; | ||
| } | ||
|
|
||
| int s5p_usb_phy_init(struct platform_device *pdev, int type) | ||
| { | ||
| if (type == S5P_USB_PHY_HOST) | ||
| return exynos4_usb_phy1_init(pdev); | ||
|
|
||
| return -EINVAL; | ||
| } | ||
|
|
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| int s5p_usb_phy_exit(struct platform_device *pdev, int type) | ||
| { | ||
| if (type == S5P_USB_PHY_HOST) | ||
| return exynos4_usb_phy1_exit(pdev); | ||
|
|
||
| return -EINVAL; | ||
| } |
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