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drm/amd/display: Add DSC delay factor workaround
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[Why]
Certain 4K high refresh rate modes requiring DSC are exhibiting top
of screen underflow corruption. Increasing the DSC delay by a factor
of 6 percent stops the underflow for most use cases.

[How]
Multiply DSC delay requirement in DML by a factor.
Add debug option to make this DSC delay factor configurable.

Reviewed-by: Alvin Lee <[email protected]>
Acked-by: Alex Hung <[email protected]>
Signed-off-by: George Shen <[email protected]>
Tested-by: Mark Broadworth <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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George Shen authored and alexdeucher committed Nov 2, 2022
1 parent 8dc3231 commit d5e0fb0
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Showing 7 changed files with 19 additions and 7 deletions.
1 change: 1 addition & 0 deletions drivers/gpu/drm/amd/display/dc/dc.h
Original file line number Diff line number Diff line change
Expand Up @@ -852,6 +852,7 @@ struct dc_debug_options {
bool enable_double_buffered_dsc_pg_support;
bool enable_dp_dig_pixel_rate_div_policy;
enum lttpr_mode lttpr_mode_override;
unsigned int dsc_delay_factor_wa_x1000;
};

struct gpu_info_soc_bounding_box_v1_0;
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4 changes: 3 additions & 1 deletion drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -2359,9 +2359,11 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

}

/* DML DSC delay factor workaround */
dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;

/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
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Original file line number Diff line number Diff line change
Expand Up @@ -367,7 +367,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
mode_lib->vba.OutputBpp[k], mode_lib->vba.HActive[k], mode_lib->vba.HTotal[k],
mode_lib->vba.NumberOfDSCSlices[k], mode_lib->vba.OutputFormat[k],
mode_lib->vba.Output[k], mode_lib->vba.PixelClock[k],
mode_lib->vba.PixelClockBackEnd[k]);
mode_lib->vba.PixelClockBackEnd[k], mode_lib->vba.ip.dsc_delay_factor_wa);
}

for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
Expand Down Expand Up @@ -2475,7 +2475,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
mode_lib->vba.OutputBppPerState[i][k], mode_lib->vba.HActive[k],
mode_lib->vba.HTotal[k], mode_lib->vba.NumberOfDSCSlices[k],
mode_lib->vba.OutputFormat[k], mode_lib->vba.Output[k],
mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k]);
mode_lib->vba.PixelClock[k], mode_lib->vba.PixelClockBackEnd[k],
mode_lib->vba.ip.dsc_delay_factor_wa);
}

for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
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Original file line number Diff line number Diff line change
Expand Up @@ -1726,7 +1726,8 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
enum output_format_class OutputFormat,
enum output_encoder_class Output,
double PixelClock,
double PixelClockBackEnd)
double PixelClockBackEnd,
double dsc_delay_factor_wa)
{
unsigned int DSCDelayRequirement_val;

Expand Down Expand Up @@ -1764,7 +1765,7 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
dml_print("DML::%s: DSCDelayRequirement_val = %d\n", __func__, DSCDelayRequirement_val);
#endif

return DSCDelayRequirement_val;
return dml_ceil(DSCDelayRequirement_val * dsc_delay_factor_wa, 1);
}

void dml32_CalculateSurfaceSizeInMall(
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Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,8 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled,
enum output_format_class OutputFormat,
enum output_encoder_class Output,
double PixelClock,
double PixelClockBackEnd);
double PixelClockBackEnd,
double dsc_delay_factor_wa);

void dml32_CalculateSurfaceSizeInMall(
unsigned int NumberOfActiveSurfaces,
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5 changes: 4 additions & 1 deletion drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@
#include "dcn321_fpu.h"
#include "dcn32/dcn32_resource.h"
#include "dcn321/dcn321_resource.h"
#include "dml/dcn32/display_mode_vba_util_32.h"

#define DCN3_2_DEFAULT_DET_SIZE 256

Expand Down Expand Up @@ -538,9 +539,11 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p

if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;

}

/* DML DSC delay factor workaround */
dcn3_21_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0;

/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */
dcn3_21_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
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3 changes: 3 additions & 0 deletions drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
Original file line number Diff line number Diff line change
Expand Up @@ -364,6 +364,9 @@ struct _vcs_dpi_ip_params_st {
unsigned int max_num_dp2p0_outputs;
unsigned int max_num_dp2p0_streams;
unsigned int VBlankNomDefaultUS;

/* DM workarounds */
double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix
};

struct _vcs_dpi_display_xfc_params_st {
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