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Merge tag 'media/v5.12-1' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - some core fixes in VB2 mem2mem support - some improvements and cleanups in V4L2 async kAPI - newer controls in V4L2 API for H-264 and HEVC codecs - allegro-dvt driver was promoted from staging - new i2c sendor drivers: imx334, ov5648, ov8865 - new automobile camera module: rdacm21 - ipu3 cio2 driver started gained support for some ACPI BIOSes - new ATSC frontend: MaxLinear mxl692 VSB tuner/demod - the SMIA/CCS driver gained more support for CSS standard - several driver fixes, updates and improvements * tag 'media/v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (362 commits) media: v4l: async: Fix kerneldoc documentation for async functions media: i2c: max9271: Add MODULE_* macros media: i2c: Kconfig: Make MAX9271 a module media: imx334: 'ret' is uninitialized, should have been PTR_ERR() media: i2c: Add imx334 camera sensor driver media: dt-bindings: media: Add bindings for imx334 media: ov8856: Configure sensor for GRBG Bayer for all modes media: i2c: imx219: Implement V4L2_CID_LINK_FREQ control media: ov5675: fix vflip/hflip control media: ipu3-cio2: Build bridge only if ACPI is enabled media: Remove the legacy v4l2-clk API media: ov6650: Use the generic clock framework media: mt9m111: Use the generic clock framework media: ov9640: Use the generic clock framework media: pxa_camera: Drop the v4l2-clk clock register media: mach-pxa: Register the camera sensor fixed-rate clock media: i2c: imx258: get clock from device properties and enable it via runtime PM media: i2c: imx258: simplify getting state container media: i2c: imx258: add support for binding via device tree media: dt-bindings: media: imx258: add bindings for IMX258 sensor ...
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Documentation/devicetree/bindings/media/allegro,al5e.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/media/allegro,al5e.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
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title: Allegro DVT Video IP Codecs Device Tree Bindings | ||
|
||
maintainers: | ||
- Michael Tretter <[email protected]> | ||
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description: |- | ||
Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may | ||
either be a H.264/H.265 encoder or H.264/H.265 decoder ip core. | ||
Each actual codec engine is controlled by a microcontroller (MCU). Host | ||
software uses a provided mailbox interface to communicate with the MCU. The | ||
MCUs share an interrupt. | ||
properties: | ||
compatible: | ||
oneOf: | ||
- items: | ||
- const: allegro,al5e-1.1 | ||
- const: allegro,al5e | ||
- items: | ||
- const: allegro,al5d-1.1 | ||
- const: allegro,al5d | ||
|
||
reg: | ||
items: | ||
- description: The registers | ||
- description: The SRAM | ||
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reg-names: | ||
items: | ||
- const: regs | ||
- const: sram | ||
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interrupts: | ||
maxItems: 1 | ||
|
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clocks: | ||
items: | ||
- description: Core clock | ||
- description: MCU clock | ||
- description: Core AXI master port clock | ||
- description: MCU AXI master port clock | ||
- description: AXI4-Lite slave port clock | ||
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clock-names: | ||
items: | ||
- const: core_clk | ||
- const: mcu_clk | ||
- const: m_axi_core_aclk | ||
- const: m_axi_mcu_aclk | ||
- const: s_axi_lite_aclk | ||
|
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required: | ||
- compatible | ||
- reg | ||
- reg-names | ||
- interrupts | ||
- clocks | ||
- clock-names | ||
|
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additionalProperties: False | ||
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examples: | ||
- | | ||
fpga { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
al5e: video-codec@a0009000 { | ||
compatible = "allegro,al5e-1.1", "allegro,al5e"; | ||
reg = <0 0xa0009000 0 0x1000>, | ||
<0 0xa0000000 0 0x8000>; | ||
reg-names = "regs", "sram"; | ||
interrupts = <0 96 4>; | ||
clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>, | ||
<&clkc 71>, <&clkc 71>, <&clkc 71>; | ||
clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk", | ||
"m_axi_mcu_aclk", "s_axi_lite_aclk"; | ||
}; | ||
}; | ||
- | | ||
fpga { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
al5d: video-codec@a0029000 { | ||
compatible = "allegro,al5d-1.1", "allegro,al5d"; | ||
reg = <0 0xa0029000 0 0x1000>, | ||
<0 0xa0020000 0 0x8000>; | ||
reg-names = "regs", "sram"; | ||
interrupts = <0 96 4>; | ||
clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>, | ||
<&clkc 71>, <&clkc 71>, <&clkc 71>; | ||
clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk", | ||
"m_axi_mcu_aclk", "s_axi_lite_aclk"; | ||
}; | ||
}; | ||
... |
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