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Verilog to Routing -- Open Source CAD Flow for FPGA Research

C++ 1,055 404 Updated Feb 22, 2025

micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop

Python 13 Updated Jan 26, 2025

A python3 gm/ID starter kit

Python 46 10 Updated Sep 6, 2024

Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outputs a compiled layout file. The default output format is JSO…

C++ 26 3 Updated Feb 21, 2025

SAR ADC on tiny tapeout

Jupyter Notebook 39 2 Updated Jan 29, 2025
PostScript 10 2 Updated Apr 22, 2021

Book repository "Analysis and Design of Elementary MOS Amplifier Stages"

Jupyter Notebook 347 18 Updated Aug 22, 2024

EM simulation scripts to simulate passive devices on Skywater 130nm open-source process. (Octave interface only for now)

MATLAB 9 Updated Jan 7, 2024

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

Verilog 312 69 Updated Feb 12, 2025

Numerically controlled oscillator for FPGA

VHDL 4 1 Updated Nov 3, 2024

Small scripts and examples to make interacting with the PlutoSDR easier

C 83 29 Updated Sep 27, 2024

A cross platform library for interfacing with local and remote Linux IIO devices

C 509 325 Updated Feb 21, 2025

Project for modernizing Emacs' Package Menu. With package ratings, usage statistics, customizability, and more.

Emacs Lisp 559 37 Updated Oct 21, 2022

VHDL compiler and simulator

VHDL 666 85 Updated Feb 22, 2025

Opulent Voice Modulator and Demodulator in C++ (GPL)

C++ 13 3 Updated May 27, 2024

gr-limesdr Plugin for GNURadio

C++ 147 77 Updated Mar 25, 2024

GNU Radio – the Free and Open Software Radio Ecosystem

C++ 5,297 1,940 Updated Feb 22, 2025

PyBOMBS (Python Build Overlay Managed Bundle System) is the GNU Radio install management system for resolving dependencies and pulling in out-of-tree projects.

Python 423 187 Updated Apr 25, 2022

Parametric layout generator for digital, analog and mixed-signal integrated circuits

C 52 6 Updated Feb 19, 2025

FasterCap is a powerful three- and two-dimensional capactiance extraction program.

C++ 23 17 Updated Oct 25, 2019

FastHenry is the premium inductance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastHenry extracts the inductances and resistances of any arbitrary…

C 57 23 Updated Dec 6, 2019

The LoRaMesher library implements a distance-vector routing protocol for communicating messages among LoRa nodes.

C++ 168 46 Updated Feb 21, 2025

Universal wireless communication library for embedded devices

C++ 1,764 433 Updated Feb 19, 2025
C 143 38 Updated Jun 9, 2024

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

HTML 467 72 Updated Feb 19, 2025

Icarus Verilog

C++ 2,957 541 Updated Feb 17, 2025

cocotb: Python-based chip (RTL) verification

Python 1,889 537 Updated Feb 19, 2025

A tiny Python package to parse spice raw data files.

Python 46 8 Updated Dec 26, 2022

Generic Process Design Kit for Gdsfactory

Python 17 4 Updated May 9, 2024

Verilator open-source SystemVerilog simulator and lint system

C++ 2,733 634 Updated Feb 21, 2025
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