ddr: marvell: a38x: allow board specific clock out setup

DDR clock out might be unrelated to the number of active chip-select. For example, the board might have two DDR components, but only one chip-select. The clk_enable mask allows the board to enable DDR clocks regardless of active chip-selects. Reviewed-by: Stefan Roese <[email protected]> Signed-off-by: Baruch Siach <[email protected]>
jrmerkel · Jan 21, 2020 · d67b98e · d67b98e
1 parent c7819d4
commit d67b98e
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Showing 2 changed files with 11 additions and 2 deletions.
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -280,8 +280,14 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
 {
 	u32 data, addr_hi, data_high;
 	u32 mem_index;
+	u32 clk_enable;
 	struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 
+	if (tm->clk_enable & (1 << cs_num))
+		clk_enable = 1;
+	else
+		clk_enable = enable;
+
 	if (enable == 1) {
 		data = (tm->interface_params[if_id].bus_width ==
 			MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
@@ -316,13 +322,13 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
 	case 2:
 		CHECK_STATUS(ddr3_tip_if_write
 			     (dev_num, ACCESS_TYPE_UNICAST, if_id,
-			      DUNIT_CTRL_LOW_REG, (enable << (cs_num + 11)),
+			      DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)),
 			      1 << (cs_num + 11)));
 		break;
 	case 3:
 		CHECK_STATUS(ddr3_tip_if_write
 			     (dev_num, ACCESS_TYPE_UNICAST, if_id,
-			      DUNIT_CTRL_LOW_REG, (enable << 15), 1 << 15));
+			      DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15));
 		break;
 	}
 

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -124,6 +124,9 @@ struct mv_ddr_topology_map {
 
 	/* electrical parameters */
 	unsigned int electrical_data[MV_DDR_EDATA_LAST];
+
+	/* Clock enable mask */
+	u32 clk_enable;
 };
 
 enum mv_ddr_iface_mode {