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NAND core changes:
- use longest matching pattern in ->exec_op() default parser
- export NAND operation tracer
- add flag to indicate panic_write in MTD
- use kzalloc() instead of kmalloc() and memset()

Raw NAND controller drivers changes:
- brcmnand:
  * fix BCH ECC layout for large page NAND parts
  * fallback to detected ecc-strength, ecc-step-size
  * when oops in progress use pio and interrupt polling
  * code refactor code to introduce helper functions
  * add support for v7.3 controller
- FSMC:
  * use nand_op_trace for operation tracing
- GPMI:
  * move all driver code into single file
  * various cleanups (including dmaengine changes)
  * use runtime PM to manage clocks
  * implement exec_op
- MTK:
  * correct low level time calculation of r/w cycle
  * improve data sampling timing for read cycle
  * add validity check for CE# pin setting
  * fix wrongly assigned OOB buffer pointer issue
  * re-license MTK NAND driver as Dual MIT/GPL
- STM32:
  * manage the get_irq error case
  * increase DMA completion timeouts

Raw NAND chips drivers changes:
- Macronix: add read-retry support

Onenand driver changes:
- add support for 8Gb datasize chips
- avoid fall-through warnings

SPI-NAND changes:
- define macros for page-read ops with three-byte addresses
- add support for two-byte device IDs and then for GigaDevice
  GD5F1GQ4UFxxG
- add initial support for Paragon PN26G0xA
- handle the case where the last page read has bitflips
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@richardweinberger
richardweinberger committed Jul 6, 2019
2 parents b07079f + bce9437 commit 1d2af80
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8 changes: 8 additions & 0 deletions CREDITS
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Expand Up @@ -3364,6 +3364,14 @@ S: Braunschweiger Strasse 79
S: 31134 Hildesheim
S: Germany

N: Martin Schwidefsky
D: Martin was the most significant contributor to the initial s390
D: port of the Linux Kernel and later the maintainer of the s390
D: architecture backend for almost two decades.
D: He passed away in 2019, and will be greatly missed.
S: Germany
W: https://lwn.net/Articles/789028/

N: Marcel Selhorst
E: [email protected]
D: TPM driver
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29 changes: 0 additions & 29 deletions Documentation/ABI/testing/sysfs-bus-mdio
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19 changes: 13 additions & 6 deletions Documentation/ABI/testing/sysfs-class-net-phydev
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Expand Up @@ -11,24 +11,31 @@ Date: February 2014
KernelVersion: 3.15
Contact: [email protected]
Description:
Boolean value indicating whether the PHY device has
any fixups registered against it (phy_register_fixup)
This attribute contains the boolean value whether a given PHY
device has had any "fixup" workaround running on it, encoded as
a boolean. This information is provided to help troubleshooting
PHY configurations.

What: /sys/class/mdio_bus/<bus>/<device>/phy_id
Date: November 2012
KernelVersion: 3.8
Contact: [email protected]
Description:
32-bit hexadecimal value corresponding to the PHY device's OUI,
model and revision number.
This attribute contains the 32-bit PHY Identifier as reported
by the device during bus enumeration, encoded in hexadecimal.
This ID is used to match the device with the appropriate
driver.

What: /sys/class/mdio_bus/<bus>/<device>/phy_interface
Date: February 2014
KernelVersion: 3.15
Contact: [email protected]
Description:
String value indicating the PHY interface, possible
values are:.
This attribute contains the PHY interface as configured by the
Ethernet driver during bus enumeration, encoded in string.
This interface mode is used to configure the Ethernet MAC with the
appropriate mode for its data lines to the PHY hardware.
Possible values are:
<empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
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9 changes: 9 additions & 0 deletions Documentation/admin-guide/cgroup-v2.rst
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Expand Up @@ -177,6 +177,15 @@ cgroup v2 currently supports the following mount options.
ignored on non-init namespace mounts. Please refer to the
Delegation section for details.

memory_localevents

Only populate memory.events with data for the current cgroup,
and not any subtrees. This is legacy behaviour, the default
behaviour without this option is to include subtree counts.
This option is system wide and can only be set on mount or
modified through remount from the init namespace. The mount
option is ignored on non-init namespace mounts.


Organizing Processes and Threads
--------------------------------
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1 change: 1 addition & 0 deletions Documentation/admin-guide/mm/index.rst
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Expand Up @@ -31,6 +31,7 @@ the Linux memory management.
ksm
memory-hotplug
numa_memory_policy
numaperf
pagemap
soft-dirty
transhuge
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2 changes: 1 addition & 1 deletion Documentation/admin-guide/mm/numaperf.rst
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Expand Up @@ -15,7 +15,7 @@ characteristics. Some memory may share the same node as a CPU, and others
are provided as memory only nodes. While memory only nodes do not provide
CPUs, they may still be local to one or more compute nodes relative to
other nodes. The following diagram shows one such example of two compute
nodes with local memory and a memory only node for each of compute node:
nodes with local memory and a memory only node for each of compute node::

+------------------+ +------------------+
| Compute Node 0 +-----+ Compute Node 1 |
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9 changes: 5 additions & 4 deletions Documentation/arm64/silicon-errata.txt
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Expand Up @@ -58,13 +58,14 @@ stable kernels.
| ARM | Cortex-A72 | #853709 | N/A |
| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 |
| ARM | Cortex-A76 | #1188873 | ARM64_ERRATUM_1188873 |
| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
| ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 |
| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
| ARM | Neoverse-N1 | #1188873 | ARM64_ERRATUM_1188873 |
| ARM | MMU-500 | #841119,#826419 | N/A |
| ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 |
| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
| ARM | MMU-500 | #841119,826419 | N/A |
| | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
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2 changes: 1 addition & 1 deletion Documentation/bpf/btf.rst
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Expand Up @@ -131,7 +131,7 @@ The following sections detail encoding of each kind.
``btf_type`` is followed by a ``u32`` with the following bits arrangement::

#define BTF_INT_ENCODING(VAL) (((VAL) & 0x0f000000) >> 24)
#define BTF_INT_OFFSET(VAL) (((VAL & 0x00ff0000)) >> 16)
#define BTF_INT_OFFSET(VAL) (((VAL) & 0x00ff0000) >> 16)
#define BTF_INT_BITS(VAL) ((VAL) & 0x000000ff)

The ``BTF_INT_ENCODING`` has the following attributes::
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2 changes: 1 addition & 1 deletion Documentation/conf.py
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Expand Up @@ -37,7 +37,7 @@
extensions = ['kerneldoc', 'rstFlatTable', 'kernel_include', 'cdomain', 'kfigure', 'sphinx.ext.ifconfig']

# The name of the math extension changed on Sphinx 1.4
if major == 1 and minor > 3:
if (major == 1 and minor > 3) or (major > 1):
extensions.append("sphinx.ext.imgmath")
else:
extensions.append("sphinx.ext.pngmath")
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/Makefile
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Expand Up @@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)

quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \
cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
$(DT_EXTRACT_EX) $< > $@

$(obj)/%.example.dts: $(src)/%.yaml FORCE
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4 changes: 2 additions & 2 deletions Documentation/devicetree/bindings/arm/arm-boards
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Expand Up @@ -216,7 +216,7 @@ Example:
#size-cells = <0>;

A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -225,7 +225,7 @@ Example:
.....

A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
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12 changes: 6 additions & 6 deletions Documentation/devicetree/bindings/arm/cpu-capacity.txt
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Expand Up @@ -118,7 +118,7 @@ cpus {
};

A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -129,7 +129,7 @@ cpus {
};

A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -140,7 +140,7 @@ cpus {
};

A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -151,7 +151,7 @@ cpus {
};

A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -162,7 +162,7 @@ cpus {
};

A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
Expand All @@ -173,7 +173,7 @@ cpus {
};

A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/arm/omap/crossbar.txt
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Expand Up @@ -41,7 +41,7 @@ Examples:
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
further details.

An interrupt consumer on an SoC using crossbar will use:
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
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Expand Up @@ -35,7 +35,7 @@ board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.

[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml

Example: Clock controller node:

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24 changes: 13 additions & 11 deletions Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
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Expand Up @@ -92,6 +92,8 @@ properties:
minItems: 2
maxItems: 4

ranges: true

interrupts:
description: Interrupt source of the parent interrupt controller on
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
Expand Down Expand Up @@ -197,28 +199,28 @@ examples:
interrupt-controller@e1101000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
interrupts = <1 8 0xf04>;
ranges = <0 0 0 0xe1100000 0 0x100000>;
reg = <0x0 0xe1110000 0 0x01000>,
<0x0 0xe112f000 0 0x02000>,
<0x0 0xe1140000 0 0x10000>,
<0x0 0xe1160000 0 0x10000>;
ranges = <0 0xe1100000 0x100000>;
reg = <0xe1110000 0x01000>,
<0xe112f000 0x02000>,
<0xe1140000 0x10000>,
<0xe1160000 0x10000>;
v2m0: v2m@8000 {
v2m0: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x80000 0 0x1000>;
reg = <0x80000 0x1000>;
};
//...
v2mN: v2m@9000 {
v2mN: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x90000 0 0x1000>;
reg = <0x90000 0x1000>;
};
};
...
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt
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Expand Up @@ -23,7 +23,7 @@ Required properties:
- marvell,spi-base : List of GIC base SPI interrupts, one for each
ODMI frame. Those SPI interrupts are 0-based,
i.e marvell,spi-base = <128> will use SPI #96.
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details about the GIC Device Tree binding.

Example:
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/leds/irled/spi-ir-led.txt
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Expand Up @@ -15,7 +15,7 @@ Optional properties:
- power-supply: specifies the power source. It can either be a regulator
or a gpio which enables a regulator, i.e. a regulator-fixed as
described in
Documentation/devicetree/bindings/regulator/fixed-regulator.txt
Documentation/devicetree/bindings/regulator/fixed-regulator.yaml

Example:

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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
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Expand Up @@ -24,7 +24,7 @@ Optional children nodes:
Children nodes represent the available nand chips.

Other properties:
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.

Example demonstrate on AXG SoC:

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7 changes: 4 additions & 3 deletions Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt
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Expand Up @@ -28,6 +28,7 @@ Required properties:
brcm,brcmnand-v7.0
brcm,brcmnand-v7.1
brcm,brcmnand-v7.2
brcm,brcmnand-v7.3
brcm,brcmnand
- reg : the register start and length for NAND register region.
(optional) Flash DMA register range (if present)
Expand Down Expand Up @@ -101,12 +102,12 @@ Required properties:
number (e.g., 0, 1, 2, etc.)
- #address-cells : see partition.txt
- #size-cells : see partition.txt
- nand-ecc-strength : see nand.txt
- nand-ecc-step-size : must be 512 or 1024. See nand.txt

Optional properties:
- nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
chip-select. See nand.txt
chip-select. See nand-controller.yaml
- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
expected for the ECC layout in use. This size, in
addition to the strength and step-size,
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6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/denali-nand.txt
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Expand Up @@ -22,16 +22,16 @@ Sub-nodes:
select is connected.

Optional properties:
- nand-ecc-step-size: see nand.txt for details.
- nand-ecc-step-size: see nand-controller.yaml for details.
If present, the value must be
512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-strength: see nand.txt for details. Valid values are:
- nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-maximize: see nand.txt for details
- nand-ecc-maximize: see nand-controller.yaml for details

The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
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6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/mtd/fsmc-nand.txt
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Expand Up @@ -30,9 +30,9 @@ Optional properties:
command is asserted. Zero means one cycle, 255 means 256
cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default).
- nand-ecc-mode : see nand.txt
- nand-ecc-strength : see nand.txt
- nand-ecc-step-size : see nand.txt
- nand-ecc-mode : see nand-controller.yaml
- nand-ecc-strength : see nand-controller.yaml
- nand-ecc-step-size : see nand-controller.yaml

Can support 1-bit HW ECC (default) or if stronger correction is required,
software-based BCH.
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2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/mtd/gpmc-nand.txt
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Expand Up @@ -8,7 +8,7 @@ explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt

For NAND specific properties such as ECC modes or bus width, please refer to
Documentation/devicetree/bindings/mtd/nand.txt
Documentation/devicetree/bindings/mtd/nand-controller.yaml


Required properties:
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