Learning FPGA, yosys, nextpnr, and RISC-V

Configurable RISC-V Processor

Python-based Hardware Design Processing Toolkit for Verilog HDL

Full Speed USB DFU interface for FPGA and ASIC designs

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license

RISC-V Linux SoC, marchID: 0x2b

A FPGA friendly 32 bit RISC-V CPU implementation

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

LLM training in simple, raw C/CUDA

Polar coding, decoding, and testing

Must-have verilog systemverilog modules

slamplay is a collection of powerful tools to start playing and experimenting with SLAM in C++

MIPS CPU implemented in Verilog

C++ library to implement invariant extended Kalman filtering for aided inertial navigation.

Verilog Ethernet components for FPGA implementation

HDL libraries and projects

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

NCTU 2021 Spring Integrated Circuit Design Laboratory

SG90稳定平台

MPU6050 Triple Axis Gyroscope & Accelerometer Arduino Library

Numerical differential equation solvers in JAX. Autodifferentiable and GPU-capable. https://docs.kidger.site/diffrax/

Model-predictive control for microcontrollers

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

Robotics with GPU computing