Convert remaining code to using newly introduced integer sized types

Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies.  We also convert the PRI printf formatters in the arch
code over to normal formatters.

Jira: ZEP-2051

Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <[email protected]>

arch/arc/core/fault.c

@@ -53,7 +53,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 	u32_t exc_addr = _arc_v2_aux_reg_read(_ARC_V2_EFA);
 	u32_t ecr = _arc_v2_aux_reg_read(_ARC_V2_ECR);
 
-	PR_EXC("Exception vector: 0x%x, cause code: 0x%x, parameter 0x%xn",
+	PR_EXC("Exception vector: 0x%x, cause code: 0x%x, parameter 0x%x\n",
 	       _ARC_V2_ECR_VECTOR(ecr),
 	       _ARC_V2_ECR_CODE(ecr),
 	       _ARC_V2_ECR_PARAMETER(ecr));

arch/arc/core/irq_manage.c

@@ -74,7 +74,7 @@ void _arch_irq_disable(unsigned int irq)
  * @return N/A
  */
 
-void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 {
 	ARG_UNUSED(flags);
 

arch/arm/core/cortex_m/exc_manage.c

@@ -15,24 +15,23 @@
 #include <misc/printk.h>
 void sys_exc_esf_dump(NANO_ESF *esf)
 {
-	printk("r0/a1:  %" PRIx32 "  ", esf->a1);
-	printk("r1/a2:  %" PRIx32 "  ", esf->a2);
-	printk("r2/a3:  %" PRIx32 "\n", esf->a3);
-	printk("r3/a4:  %" PRIx32 "  ", esf->a4);
-	printk("r12/ip: %" PRIx32 "  ", esf->ip);
-	printk("r14/lr: %" PRIx32 "\n", esf->lr);
-	printk("r15/pc: %" PRIx32 "  ", esf->pc);
-	printk("xpsr:   %" PRIx32 "\n", esf->xpsr);
+	printk("r0/a1:  %x  ", esf->a1);
+	printk("r1/a2:  %x  ", esf->a2);
+	printk("r2/a3:  %x\n", esf->a3);
+	printk("r3/a4:  %x  ", esf->a4);
+	printk("r12/ip: %x  ", esf->ip);
+	printk("r14/lr: %x\n", esf->lr);
+	printk("r15/pc: %x  ", esf->pc);
+	printk("xpsr:   %x\n", esf->xpsr);
 #ifdef CONFIG_FLOAT
 	for (int i = 0; i < 16; i += 4) {
-		printk("s[%d]:  %" PRIx32 "  s[%d]:  %" PRIx32 "  s[%d]:  %"
-		       PRIx32 "  s[%d]:  %" PRIx32 "\n",
-		       i, (uint32_t)esf->s[i],
-		       i + 1, (uint32_t)esf->s[i + 1],
-		       i + 2, (uint32_t)esf->s[i + 2],
-		       i + 3, (uint32_t)esf->s[i + 3]);
+		printk("s[%d]:  %x  s[%d]:  %x  s[%d]:  %x  s[%d]:  %x\n",
+		       i, (u32_t)esf->s[i],
+		       i + 1, (u32_t)esf->s[i + 1],
+		       i + 2, (u32_t)esf->s[i + 2],
+		       i + 3, (u32_t)esf->s[i + 3]);
 	}
-	printk("fpscr:  %" PRIx32 "\n", esf->fpscr);
+	printk("fpscr:  %x\n", esf->fpscr);
 #endif
 }
 

arch/arm/core/fatal.c

@@ -89,7 +89,7 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 		break;
 	}
 	PR_EXC("Current thread ID = %p\n"
-	       "Faulting instruction address = 0x%" PRIx32 "\n",
+	       "Faulting instruction address = 0x%x\n",
 	       k_current_get(), pEsf->pc);
 
 	/*

arch/arm/core/fault.c

@@ -54,7 +54,7 @@
  */
 void _FaultDump(const NANO_ESF *esf, int fault)
 {
-	PR_EXC("Fault! EXC #%d, Thread: %p, instr @ 0x%" PRIx32 "\n",
+	PR_EXC("Fault! EXC #%d, Thread: %p, instr @ 0x%x\n",
 	       fault,
 	       k_current_get(),
 	       esf->pc);
@@ -70,18 +70,18 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 				  : "Bus fault on vector table read\n");
 	}
 
-	PR_EXC("MMFSR: 0x%" PRIx32 ", BFSR: 0x%" PRIx32 ", UFSR: 0x%"
-	       PRIx32 "\n", SCB_MMFSR, SCB_BFSR, SCB_MMFSR);
+	PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x\n",
+	       SCB_MMFSR, SCB_BFSR, SCB_MMFSR);
 
 	if (SCB->CFSR & CFSR_MMARVALID_Msk) {
-		PR_EXC("MMFAR: 0x%" PRIx32 "\n", SCB->MMFAR);
+		PR_EXC("MMFAR: 0x%x\n", SCB->MMFAR);
 		if (escalation) {
 			/* clear MMAR[VALID] to reset */
 			SCB->CFSR &= ~CFSR_MMARVALID_Msk;
 		}
 	}
 	if (SCB->CFSR & CFSR_BFARVALID_Msk) {
-		PR_EXC("BFAR: 0x%" PRIx32 "\n", SCB->BFAR);
+		PR_EXC("BFAR: 0x%x\n", SCB->BFAR);
 		if (escalation) {
 			/* clear CFSR_BFAR[VALID] to reset */
 			SCB->CFSR &= ~CFSR_BFARVALID_Msk;
@@ -108,7 +108,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 static void _FaultThreadShow(const NANO_ESF *esf)
 {
 	PR_EXC("  Executing thread ID (thread): %p\n"
-	       "  Faulting instruction address:  0x%" PRIx32 "\n",
+	       "  Faulting instruction address:  0x%x\n",
 	       k_current_get(), esf->pc);
 }
 
@@ -136,7 +136,7 @@ static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
 	} else if (SCB->CFSR & CFSR_DACCVIOL_Msk) {
 		PR_EXC("  Data Access Violation\n");
 		if (SCB->CFSR & CFSR_MMARVALID_Msk) {
-			PR_EXC("  Address: 0x%" PRIx32 "\n", SCB->MMFAR);
+			PR_EXC("  Address: 0x%x\n", (u32_t)SCB->MMFAR);
 			if (fromHardFault) {
 				/* clear MMAR[VALID] to reset */
 				SCB->CFSR &= ~CFSR_MMARVALID_Msk;
@@ -168,7 +168,7 @@ static void _BusFault(const NANO_ESF *esf, int fromHardFault)
 	} else if (SCB->CFSR & CFSR_PRECISERR_Msk) {
 		PR_EXC("  Precise data bus error\n");
 		if (SCB->CFSR & CFSR_BFARVALID_Msk) {
-			PR_EXC("  Address: 0x%" PRIx32 "\n", SCB->BFAR);
+			PR_EXC("  Address: 0x%x\n", (u32_t)SCB->BFAR);
 			if (fromHardFault) {
 				/* clear CFSR_BFAR[VALID] to reset */
 				SCB->CFSR &= ~CFSR_BFARVALID_Msk;

arch/arm/core/irq_manage.c

@@ -82,7 +82,7 @@ int _arch_irq_is_enabled(unsigned int irq)
  *
  * @return N/A
  */
-void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
 {
 	/* Hardware priority levels 0 and 1 reserved for Kernel use.
 	 * So we add 2 to the requested priority level. If we support

arch/nios2/core/fatal.c

@@ -78,16 +78,12 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 	 * registers, at the expense of some stack space.
 	 */
 	printk("Current thread ID: %p\n"
-	       "Faulting instruction: 0x%" PRIx32 "\n"
-	       "  r1: 0x%" PRIx32 "  r2: 0x%" PRIx32
-	       "  r3: 0x%" PRIx32 "  r4: 0x%" PRIx32 "\n"
-	       "  r5: 0x%" PRIx32 "  r6: 0x%" PRIx32
-	       "  r7: 0x%" PRIx32 "  r8: 0x%" PRIx32 "\n"
-	       "  r9: 0x%" PRIx32 " r10: 0x%" PRIx32
-	       " r11: 0x%" PRIx32 " r12: 0x%" PRIx32 "\n"
-	       " r13: 0x%" PRIx32 " r14: 0x%" PRIx32
-	       " r15: 0x%" PRIx32 "  ra: 0x%" PRIx32 "\n"
-	       "estatus: %" PRIx32 "\n", k_current_get(), esf->instr - 4,
+	       "Faulting instruction: 0x%x\n"
+	       "  r1: 0x%x  r2: 0x%x  r3: 0x%x  r4: 0x%x\n"
+	       "  r5: 0x%x  r6: 0x%x  r7: 0x%x  r8: 0x%x\n"
+	       "  r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n"
+	       " r13: 0x%x r14: 0x%x r15: 0x%x  ra: 0x%x\n"
+	       "estatus: %x\n", k_current_get(), esf->instr - 4,
 	       esf->r1, esf->r2, esf->r3, esf->r4,
 	       esf->r5, esf->r6, esf->r7, esf->r8,
 	       esf->r9, esf->r10, esf->r11, esf->r12,

arch/riscv32/core/fatal.c

@@ -91,16 +91,12 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
 	}
 
 	PRINTK("Current thread ID = %p\n"
-	       "Faulting instruction address = 0x%" PRIx32 "\n"
-	       "  ra: 0x%" PRIx32 "  gp: 0x%" PRIx32
-	       "  tp: 0x%" PRIx32 "  t0: 0x%" PRIx32 "\n"
-	       "  t1: 0x%" PRIx32 "  t2: 0x%" PRIx32
-	       "  t3: 0x%" PRIx32 "  t4: 0x%" PRIx32 "\n"
-	       "  t5: 0x%" PRIx32 "  t6: 0x%" PRIx32
-	       "  a0: 0x%" PRIx32 "  a1: 0x%" PRIx32 "\n"
-	       "  a2: 0x%" PRIx32 "  a3: 0x%" PRIx32
-	       "  a4: 0x%" PRIx32 "  a5: 0x%" PRIx32 "\n"
-	       "  a6: 0x%" PRIx32 "  a7: 0x%" PRIx32 "\n",
+	       "Faulting instruction address = 0x%x\n"
+	       "  ra: 0x%x  gp: 0x%x  tp: 0x%x  t0: 0x%x\n"
+	       "  t1: 0x%x  t2: 0x%x  t3: 0x%x  t4: 0x%x\n"
+	       "  t5: 0x%x  t6: 0x%x  a0: 0x%x  a1: 0x%x\n"
+	       "  a2: 0x%x  a3: 0x%x  a4: 0x%x  a5: 0x%x\n"
+	       "  a6: 0x%x  a7: 0x%x\n",
 	       k_current_get(),
 	       (esf->mepc == 0xdeadbaad) ? 0xdeadbaad : esf->mepc - 4,
 	       esf->ra, esf->gp, esf->tp, esf->t0,

arch/x86/core/fatal.c

@@ -192,7 +192,7 @@ FUNC_NORETURN void page_fault_handler(const NANO_ESF *pEsf)
 	err = pEsf->errorCode;
 	printk("***** CPU Page Fault (error code 0x%08x)\n", err);
 
-	printk("%s thread %s address 0x%08" PRIx32 "\n",
+	printk("%s thread %s address 0x%08x\n",
 	       err & US ? "User" : "Supervisor",
 	       err & ID ? "executed" : (err & WR ? "wrote" : "read"),
 	       cr2);

drivers/grove/lcd_rgb.c

@@ -102,7 +102,7 @@ static inline void _sleep(u32_t sleep_in_ms)
 /********************************************
  *  PUBLIC FUNCTIONS
  *******************************************/
-void glcd_print(struct device *port, char *data, uint32_t size)
+void glcd_print(struct device *port, char *data, u32_t size)
 {
 	const struct glcd_driver * const rom = (struct glcd_driver *)
 						port->config->config_info;

drivers/i2c/i2c_atmel_sam3.c

@@ -184,7 +184,7 @@ static u32_t clk_div_calc(struct device *dev)
 #endif /* CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 84000000 */
 }
 
-static int i2c_sam3_runtime_configure(struct device *dev, uint32_t config)
+static int i2c_sam3_runtime_configure(struct device *dev, u32_t config)
 {
 	const struct i2c_sam3_dev_config * const cfg = dev->config->config_info;
 	struct i2c_sam3_dev_data * const dev_data = dev->driver_data;

drivers/i2c/i2c_qmsi_ss.c

@@ -219,7 +219,7 @@ static void i2c_qmsi_ss_config_irq_1(void)
 }
 #endif /* CONFIG_I2C_SS_1 */
 
-static int i2c_qmsi_ss_configure(struct device *dev, uint32_t config)
+static int i2c_qmsi_ss_configure(struct device *dev, u32_t config)
 {
 	qm_ss_i2c_t instance = GET_CONTROLLER_INSTANCE(dev);
 	struct i2c_qmsi_ss_driver_data *driver_data = GET_DRIVER_DATA(dev);

drivers/timer/altera_avalon_timer.c

@@ -96,7 +96,7 @@ int _sys_clock_driver_init(struct device *device)
 }
 
 
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	/* XXX Per the Altera Embedded IP Peripherals guide, you cannot
 	 * use a timer instance for both the system clock and timestamps

drivers/timer/arcv2_timer0.c

@@ -413,7 +413,7 @@ int sys_clock_device_ctrl(struct device *port, u32_t ctrl_command,
 }
 #endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
 
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	u32_t acc, count;
 

drivers/timer/cortex_m_systick.c

@@ -557,7 +557,7 @@ int _sys_clock_driver_init(struct device *device)
  * systick counter is a 24-bit down counter which is reset to "reload" value
  * once it reaches 0.
  */
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	u32_t cac, count;
 

drivers/timer/hpet.c

@@ -593,7 +593,7 @@ int _sys_clock_driver_init(struct device *device)
  * it will need to call _hpetMainCounterAtomic().
  */
 
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	return (u32_t) *_HPET_MAIN_COUNTER_VALUE;
 }

drivers/timer/loapic_timer.c

@@ -581,7 +581,7 @@ int sys_clock_device_ctrl(struct device *port, u32_t ctrl_command,
  *
  * @return up counter of elapsed clock cycles
  */
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 #if CONFIG_TSC_CYCLES_PER_SEC != 0
 	u64_t tsc;

drivers/timer/nrf_rtc_timer.c

@@ -305,7 +305,7 @@ int _sys_clock_driver_init(struct device *device)
 	return 0;
 }
 
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	u32_t elapsed_cycles;
 

drivers/timer/pulpino_timer.c

@@ -68,7 +68,7 @@ int _sys_clock_driver_init(struct device *device)
  *
  * @return up counter of elapsed clock cycles
  */
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	return accumulated_cycle_count + timer->val;
 }

drivers/timer/riscv_machine_timer.c

@@ -97,7 +97,7 @@ int _sys_clock_driver_init(struct device *device)
  *
  * @return up counter of elapsed clock cycles
  */
-uint32_t _timer_cycle_get_32(void)
+u32_t _timer_cycle_get_32(void)
 {
 	/* We just want a cycle count so just post what's in the low 32
 	 * bits of the mtime real-time counter

include/adc.h

@@ -34,18 +34,18 @@ extern "C" {
  */
 struct adc_seq_entry {
 	/** Clock ticks delay before sampling the ADC. */
-	int32_t sampling_delay;
+	s32_t sampling_delay;
 
 	/** Buffer pointer where the sample is written.*/
-	uint8_t *buffer;
+	u8_t *buffer;
 
 	/** Length of the sampling buffer.*/
-	uint32_t buffer_length;
+	u32_t buffer_length;
 
 	/** Channel ID that should be sampled from the ADC */
-	uint8_t channel_id;
+	u8_t channel_id;
 
-	uint8_t stride[3];
+	u8_t stride[3];
 };
 
 /**
@@ -59,8 +59,8 @@ struct adc_seq_table {
 	struct adc_seq_entry *entries;
 
 	/* Number of entries in the sequence entry array. */
-	uint8_t num_entries;
-	uint8_t stride[3];
+	u8_t num_entries;
+	u8_t stride[3];
 };
 
 /**

include/aio_comparator.h

@@ -23,12 +23,12 @@ enum aio_cmp_polarity {
 
 typedef void (*aio_cmp_cb)(void *);
 
-typedef int (*aio_cmp_api_disable)(struct device *dev, uint8_t index);
+typedef int (*aio_cmp_api_disable)(struct device *dev, u8_t index);
 
-typedef int (*aio_cmp_api_configure)(struct device *dev, uint8_t index,
+typedef int (*aio_cmp_api_configure)(struct device *dev, u8_t index,
     enum aio_cmp_polarity polarity, enum aio_cmp_ref refsel,
     aio_cmp_cb cb, void *param);
-typedef uint32_t (*aio_cmp_api_get_pending_int)(struct device *dev);
+typedef u32_t (*aio_cmp_api_get_pending_int)(struct device *dev);
 
 struct aio_cmp_driver_api {
 	aio_cmp_api_disable disable;
@@ -46,7 +46,7 @@ struct aio_cmp_driver_api {
  *
  * @return 0 if successful, otherwise failed.
  */
-static inline int aio_cmp_disable(struct device *dev, uint8_t index)
+static inline int aio_cmp_disable(struct device *dev, u8_t index)
 {
 	const struct aio_cmp_driver_api *api = dev->driver_api;
 
@@ -68,7 +68,7 @@ static inline int aio_cmp_disable(struct device *dev, uint8_t index)
  *
  * @return 0 if successful, otherwise failed.
  */
-static inline int aio_cmp_configure(struct device *dev, uint8_t index,
+static inline int aio_cmp_configure(struct device *dev, u8_t index,
 				    enum aio_cmp_polarity polarity,
 				    enum aio_cmp_ref refsel,
 				    aio_cmp_cb cb, void *param)