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[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269933 91177308-0d34-0410-b5e6-96231b3b80d8
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Krzysztof Parzyszek committed May 18, 2016
1 parent da38a6d commit 8b8fb6b
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Showing 3 changed files with 35 additions and 2 deletions.
14 changes: 14 additions & 0 deletions lib/Target/Hexagon/HexagonISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2839,6 +2839,20 @@ HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// Inline Assembly Support
//===----------------------------------------------------------------------===//

TargetLowering::ConstraintType
HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'q':
case 'v':
if (Subtarget.useHVXOps())
return C_Register;
break;
}
}
return TargetLowering::getConstraintType(Constraint);
}

std::pair<unsigned, const TargetRegisterClass *>
HexagonTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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4 changes: 2 additions & 2 deletions lib/Target/Hexagon/HexagonISelLowering.h
Original file line number Diff line number Diff line change
Expand Up @@ -203,6 +203,8 @@ bool isPositiveHalfWord(SDNode *N);
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const override;

ConstraintType getConstraintType(StringRef Constraint) const override;

std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Expand All @@ -211,8 +213,6 @@ bool isPositiveHalfWord(SDNode *N);
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "o")
return InlineAsm::Constraint_o;
else if (ConstraintCode == "v")
return InlineAsm::Constraint_v;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}

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19 changes: 19 additions & 0 deletions test/CodeGen/Hexagon/inline-asm-qv.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
; RUN: llc -march=hexagon < %s | FileCheck %s

; Check that constraints q and v are handled correctly.
; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w)
; CHECK: vand
; CHECK: vmem

target triple = "hexagon"

; Function Attrs: nounwind
define void @foo(<16 x i32> %v0, <16 x i32> %v1, <16 x i32>* nocapture %p) #0 {
entry:
%0 = tail call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32> %v0, <16 x i32> %v1) #1
store <16 x i32> %0, <16 x i32>* %p, align 64
ret void
}

attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
attributes #1 = { nounwind readnone }

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