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feat(fc): add board support TXC-22211A/C(132/173) (ares-emulator#1530)
add TXC-22211A add TXC-22211C fix TXC-22211B mirror pass issue ares-emulator#755 pass issue ares-emulator#756
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| #pragma once | ||
| // JV001: 136/172 136 172 | ||
| // .--\/--. | .--\/--. | .--\/--. | ||
| // PPU A13 -> |01 28| -- GND | PPU A13 -> |01 28| -- GND | PPU A13 -> |01 28| -- GND | ||
| // CPU D5 <> |02 27| <- PPU R/W | CPU D5 <> |02 27| <- NC | CPU D0 <> |02 27| <- PPU R/W | ||
| // CPU D4 <> |03 26| -> Invert | CPU D4 <> |03 26| -> NC | CPU D1 <> |03 26| -> CIRAM A10 | ||
| // CPU D3 <> |04 25| <- PPU A11 | CPU D3 <> |04 25| <- NC | CPU D2 <> |04 25| <- PPU A11 | ||
| // CPU D2 <> |05 24| <- PPU A10 | CPU D2 <> |05 24| <- NC | CPU D3 <> |05 24| <- PPU A10 | ||
| // CPU D1 <> |06 23| -> O0 | CPU D1 <> |06 23| -> NC | CPU D4 <> |06 23| -> CHR A13 | ||
| // CPU D0 <> |07 22| -> O1 | CPU D0 <> |07 22| -> NC | CPU D5 <> |07 22| -> CHR A14 | ||
| // CPU A0 -> |08 21| -> O2 | CPU A0 -> |08 21| -> NC | CPU A0 -> |08 21| -> NC | ||
| // CPU A1 -> |09 20| -> O3 | CPU A1 -> |09 20| -> NC | CPU A1 -> |09 20| -> NC | ||
| // CPU A8 -> |10 19| -> O4 | CPU A8 -> |10 19| -> NC | CPU A8 -> |10 19| -> NC | ||
| // M2 -> |11 18| -> O5 | M2 -> |11 18| -> NC | M2 -> |11 18| -> NC | ||
| // /ROMSEL -> |12 17| <- CHR /OE | /ROMSEL -> |12 17| <- CHR /OE | /ROMSEL -> |12 17| <- CHR /OE | ||
| // CPU R/W -> |13 16| <- CPU A13 | CPU R/W -> |13 16| <- NC | CPU R/W -> |13 16| <- CPU A13 | ||
| // 5V -- |14 15| <- CPU A14 | 5V -- |14 15| <- NC | 5V -- |14 15| <- CPU A14 | ||
| // '------' | '------' | '------' | ||
| struct JV001 { | ||
| auto writePRG(n16 address, n8 data) -> void { | ||
| address &= 0xe103; | ||
| switch (address) { | ||
| case 0x4100: if (increment) { | ||
| ++reg.bit(0,3); | ||
| } else { | ||
| reg.bit(0,3) = in ^ (invert ? 0x0f : 0); | ||
| } | ||
| return; | ||
| case 0x4101: invert = data.bit(0); | ||
| return; | ||
| case 0x4102: reg.bit(4,5) = data.bit(4,5); | ||
| in = data.bit(0,3); | ||
| return; | ||
| case 0x4103: increment = data.bit(0); | ||
| return; | ||
| default: out.bit(0,3) = reg.bit(0,3); | ||
| out.bit(4,5) = reg.bit(4,5) ^ (invert ? 0x03 : 0); | ||
| return; | ||
| } | ||
| } | ||
|
|
||
| auto serialize(serializer& s) -> void { | ||
| s(reg); | ||
| s(invert); | ||
| s(in); | ||
| s(increment); | ||
| s(out); | ||
| } | ||
|
|
||
| n6 reg; | ||
| n1 invert; | ||
| n4 in; | ||
| n1 increment; | ||
| n6 out; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,91 @@ | ||
| #pragma once | ||
| // TXC 05-00002-010 | ||
| // .--\/--. | ||
| // Q2 <- |01 24| -> Q3 | ||
| // Q1 <- |02 23| -> Q4 | ||
| // Q0 <- |03 22| -> o3 | ||
| // i1 -> |04 21| <- CPU A13 (rn) | ||
| // i0 -> |05 20| <- CPU A14 (rn) | ||
| // io2 <> |06 19| -- GND | ||
| // 5V -- |07 18| <- CPU R/W (n) | ||
| // D5 <> |08 17| <- /ROMSEL (rn) | ||
| // D4 <> |09 16| <- M2 (n) | ||
| // D2 <> |10 15| <- CPU A8 (rn) | ||
| // D1 <> |11 14| <- CPU A1 (rn) | ||
| // D0 <> |12 13| <- CPU A0 (rn) | ||
| // '------' | ||
| // 36 132 173 | ||
| // .--\/--. .--\/--. .--\/--. | ||
| // NC <- |01 24| -> NC (r) PRG A15 <- |01 24| -> NC NC <- |01 24| -> NC | ||
| // (r) PRG A16 <- |02 23| -> NC (r) CHR A14 <- |02 23| -> NC *(r) CHR A15 <- |02 23| -> NC | ||
| // (r) PRG A15 <- |03 22| -> NC (r) CHR A13 <- |03 22| -> NC (r) CHR A13 <- |03 22| -> CHR A14 | ||
| // GND -> |04 21| <- CPU A13 (rn) GND -> |04 21| <- CPU A13 (fr) GND -> |04 21| <- CPU A13 (fr) | ||
| // 5V -> |05 20| <- CPU A14 (rn) 5V -> |05 20| <- CPU A14 (fr) 5V -> |05 20| <- CPU A14 (fr) | ||
| // NC <> |06 19| -- GND NC <> |06 19| -- GND NC <> |06 19| <- GND | ||
| // 5V -- |07 18| <- CPU R/W (n) 5V -- |07 18| <- CPU R/W (f) 5V -- |07 18| <- CPU R/W (f) | ||
| // NC <> |08 17| <- /ROMSEL (rn) GND <> |08 17| <- /ROMSEL (fr) GND <> |08 17| <- /ROMSEL (fr) | ||
| // NC <> |09 16| <- M2 (n) (fr) CPU D3 <> |09 16| <- M2 (f) (fr) CPU D3 <> |09 16| <- M2 (f) | ||
| // NC <> |10 15| <- CPU A8 (rn) (fr) CPU D2 <> |10 15| <- CPU A8 (fr) (fr) CPU D2 <> |10 15| <- CPU A8 (fr) | ||
| // (rn) CPU D5 <> |11 14| <- CPU A1 (rn) (fr) CPU D1 <> |11 14| <- CPU A1 (fr) (fr) CPU D1 <> |11 14| <- CPU A1 (fr) | ||
| // (rn) CPU D4 <> |12 13| <- CPU A0 (rn) (fr) CPU D0 <> |12 13| <- CPU A0 (fr) (fr) CPU D0 <> |12 13| <- CPU A0 (fr) | ||
| // '------'` '------' '------' | ||
| // 173*: TXC pin 2 was routed to CHR ROM pin 1 on a 28-pin package. | ||
| // On a UVEPROM, this is A15. | ||
| // However, no games were ever released using more than 32 KiB of CHR. | ||
| // TXC 05-00002-010: 36/132/173 | ||
| struct TXC05_00002_010 { | ||
| auto writePRG(n16 address, n8 data) -> void { | ||
| address &= 0xe103; | ||
| switch (address) { | ||
| case 0x4100: if (increment) { | ||
| ++reg.bit(0,3); | ||
| } else { | ||
| reg.bit(0,3) = in ^ (invert ? 0x0f : 0); | ||
| } | ||
| return; | ||
| case 0x4101: invert = data.bit(0); | ||
| if (overdown) { | ||
| o3 = (invert ? io2 : i0) | data.bit(5); | ||
| } else { | ||
| io2 = invert ? i1 : i0; | ||
| o3 = io2 | data.bit(5); | ||
| } | ||
| return; | ||
| case 0x4102: reg.bit(4,5) = data.bit(4,5); | ||
| in.bit(0,2) = data.bit(0,2); | ||
| in.bit(3) = in.bit(3) ^ invert; | ||
| return; | ||
| case 0x4103: increment = data.bit(0); | ||
| return; | ||
| default: out.bit(0,3) = reg.bit(0,3); | ||
| out.bit(4) = reg.bit(4) ^ invert; | ||
| return; | ||
| } | ||
| } | ||
|
|
||
| auto serialize(serializer& s) -> void { | ||
| s(i0); | ||
| s(i1); | ||
| s(io2); | ||
| s(o3); | ||
|
|
||
| s(increment); | ||
| s(invert); | ||
| s(overdown); | ||
| s(reg); | ||
| s(in); | ||
| s(out); | ||
| } | ||
|
|
||
| bool overdown; // io2 is using input or output flag | ||
|
|
||
| // 4 pin | ||
| n1 i0, i1, io2, o3; | ||
|
|
||
| n1 increment; | ||
| n1 invert; | ||
| n6 reg; | ||
| n4 in; | ||
| n5 out; | ||
| }; | ||
|
|
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