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Showing results

cadence virtuoso exp by lbrce student

1 Updated Jun 24, 2024

VHDL synthesis (based on ghdl)

VHDL 325 33 Updated Feb 16, 2025

[NeurIPS 2024] Depth Anything V2. A More Capable Foundation Model for Monocular Depth Estimation

Python 4,774 424 Updated Jan 22, 2025

Truly independent web browser

C++ 33,777 1,410 Updated Mar 4, 2025

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Tcl 83 16 Updated Jan 29, 2025

Generic Register Interface (contains various adapters)

SystemVerilog 109 25 Updated Sep 25, 2024

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

Verilog 56 5 Updated Mar 3, 2025

cadence virtuoso exp by lbrce student

1 Updated Jun 23, 2024

cadence virtuoso exp by lbrce student

1 Updated Jun 23, 2024

cadence virtuoso

1 Updated Jun 21, 2024

these is my third experiment

1 Updated Jun 21, 2024

Config files for my GitHub profile.

1 Updated Jun 20, 2024
HTML 1 Updated Jun 13, 2024
HTML 1 Updated Jun 12, 2024
CSS 1 Updated Jun 17, 2024

my first experiment in cadence virtuoso

1 Updated Jun 20, 2024

this is my 2nd experiment in cadence virtuoso

1 Updated Jun 20, 2024