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Merge tag 'v6.3-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/…
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…herbert/crypto-2.6

Pull crypto update from Herbert Xu:
 "API:
   - Use kmap_local instead of kmap_atomic
   - Change request callback to take void pointer
   - Print FIPS status in /proc/crypto (when enabled)

  Algorithms:
   - Add rfc4106/gcm support on arm64
   - Add ARIA AVX2/512 support on x86

  Drivers:
   - Add TRNG driver for StarFive SoC
   - Delete ux500/hash driver (subsumed by stm32/hash)
   - Add zlib support in qat
   - Add RSA support in aspeed"

* tag 'v6.3-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (156 commits)
  crypto: x86/aria-avx - Do not use avx2 instructions
  crypto: aspeed - Fix modular aspeed-acry
  crypto: hisilicon/qm - fix coding style issues
  crypto: hisilicon/qm - update comments to match function
  crypto: hisilicon/qm - change function names
  crypto: hisilicon/qm - use min() instead of min_t()
  crypto: hisilicon/qm - remove some unused defines
  crypto: proc - Print fips status
  crypto: crypto4xx - Call dma_unmap_page when done
  crypto: octeontx2 - Fix objects shared between several modules
  crypto: nx - Fix sparse warnings
  crypto: ecc - Silence sparse warning
  tls: Pass rec instead of aead_req into tls_encrypt_done
  crypto: api - Remove completion function scaffolding
  tls: Remove completion function scaffolding
  tipc: Remove completion function scaffolding
  net: ipv6: Remove completion function scaffolding
  net: ipv4: Remove completion function scaffolding
  net: macsec: Remove completion function scaffolding
  dm: Remove completion function scaffolding
  ...
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torvalds committed Feb 22, 2023
2 parents 6930840 + 8b84475 commit 36289a0
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Showing 186 changed files with 6,379 additions and 4,053 deletions.
4 changes: 2 additions & 2 deletions Documentation/ABI/testing/sysfs-driver-qat
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
What: /sys/bus/pci/devices/<BDF>/qat/state
Date: June 2022
KernelVersion: 5.20
KernelVersion: 6.0
Contact: [email protected]
Description: (RW) Reports the current state of the QAT device. Write to
the file to start or stop the device.
Expand All @@ -18,7 +18,7 @@ Description: (RW) Reports the current state of the QAT device. Write to

What: /sys/bus/pci/devices/<BDF>/qat/cfg_services
Date: June 2022
KernelVersion: 5.20
KernelVersion: 6.0
Contact: [email protected]
Description: (RW) Reports the current configuration of the QAT device.
Write to the file to change the configured services.
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37 changes: 37 additions & 0 deletions Documentation/devicetree/bindings/bus/aspeed,ast2600-ahbc.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED Advanced High-Performance Bus Controller (AHBC)

maintainers:
- Neal Liu <[email protected]>
- Chia-Wei Wang <[email protected]>

description: |
Advanced High-performance Bus Controller (AHBC) supports plenty of mechanisms
including a priority arbiter, an address decoder and a data multiplexer
to control the overall operations of Advanced High-performance Bus (AHB).
properties:
compatible:
enum:
- aspeed,ast2600-ahbc

reg:
maxItems: 1

required:
- compatible
- reg

additionalProperties: false

examples:
- |
ahbc@1e600000 {
compatible = "aspeed,ast2600-ahbc";
reg = <0x1e600000 0x100>;
};
33 changes: 25 additions & 8 deletions Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ properties:
enum:
- allwinner,sun8i-h3-crypto
- allwinner,sun8i-r40-crypto
- allwinner,sun20i-d1-crypto
- allwinner,sun50i-a64-crypto
- allwinner,sun50i-h5-crypto
- allwinner,sun50i-h6-crypto
Expand All @@ -29,13 +30,15 @@ properties:
- description: Bus clock
- description: Module clock
- description: MBus clock
- description: TRNG clock (RC oscillator)
minItems: 2

clock-names:
items:
- const: bus
- const: mod
- const: ram
- const: trng
minItems: 2

resets:
Expand All @@ -44,19 +47,33 @@ properties:
if:
properties:
compatible:
const: allwinner,sun50i-h6-crypto
enum:
- allwinner,sun20i-d1-crypto
then:
properties:
clocks:
minItems: 3
minItems: 4
clock-names:
minItems: 3
minItems: 4
else:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
if:
properties:
compatible:
const: allwinner,sun50i-h6-crypto
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
minItems: 3
maxItems: 3
else:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2

required:
- compatible
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49 changes: 49 additions & 0 deletions Documentation/devicetree/bindings/crypto/aspeed,ast2600-acry.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines

maintainers:
- Neal Liu <[email protected]>

description:
The ACRY ECDSA/RSA engines is designed to accelerate the throughput
of ECDSA/RSA signature and verification. Basically, ACRY can be
divided into two independent engines - ECC Engine and RSA Engine.

properties:
compatible:
enum:
- aspeed,ast2600-acry

reg:
items:
- description: acry base address & size
- description: acry sram base address & size

clocks:
maxItems: 1

interrupts:
maxItems: 1

required:
- compatible
- reg
- clocks
- interrupts

additionalProperties: false

examples:
- |
#include <dt-bindings/clock/ast2600-clock.h>
acry: crypto@1e6fa000 {
compatible = "aspeed,ast2600-acry";
reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
interrupts = <160>;
clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
};
23 changes: 22 additions & 1 deletion Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -6,12 +6,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 HASH

description: The STM32 HASH block is built on the HASH block found in
the STn8820 SoC introduced in 2007, and subsequently used in the U8500
SoC in 2010.

maintainers:
- Lionel Debieve <[email protected]>

properties:
compatible:
enum:
- st,stn8820-hash
- stericsson,ux500-hash
- st,stm32f456-hash
- st,stm32f756-hash

Expand Down Expand Up @@ -41,11 +47,26 @@ properties:
maximum: 2
default: 0

power-domains:
maxItems: 1

required:
- compatible
- reg
- clocks
- interrupts

allOf:
- if:
properties:
compatible:
items:
const: stericsson,ux500-hash
then:
properties:
interrupts: false
else:
required:
- interrupts

additionalProperties: false

Expand Down
55 changes: 55 additions & 0 deletions Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive SoC TRNG Module

maintainers:
- Jia Jie Ho <[email protected]>

properties:
compatible:
const: starfive,jh7110-trng

reg:
maxItems: 1

clocks:
items:
- description: Hardware reference clock
- description: AHB reference clock

clock-names:
items:
- const: hclk
- const: ahb

resets:
maxItems: 1

interrupts:
maxItems: 1

required:
- compatible
- reg
- clocks
- clock-names
- resets
- interrupts

additionalProperties: false

examples:
- |
rng: rng@1600C000 {
compatible = "starfive,jh7110-trng";
reg = <0x1600C000 0x4000>;
clocks = <&clk 15>, <&clk 16>;
clock-names = "hclk", "ahb";
resets = <&reset 3>;
interrupts = <30>;
};
...
8 changes: 7 additions & 1 deletion MAINTAINERS
Original file line number Diff line number Diff line change
Expand Up @@ -3149,7 +3149,7 @@ ASPEED CRYPTO DRIVER
M: Neal Liu <[email protected]>
L: [email protected] (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/crypto/aspeed,ast2500-hace.yaml
F: Documentation/devicetree/bindings/crypto/aspeed,*
F: drivers/crypto/aspeed/

ASUS NOTEBOOKS AND EEEPC ACPI/WMI EXTRAS DRIVERS
Expand Down Expand Up @@ -19769,6 +19769,12 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
F: drivers/reset/reset-starfive-jh7100.c
F: include/dt-bindings/reset/starfive-jh7100.h

STARFIVE TRNG DRIVER
M: Jia Jie Ho <[email protected]>
S: Supported
F: Documentation/devicetree/bindings/rng/starfive*
F: drivers/char/hw_random/jh7110-trng.c

STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
M: Josh Poimboeuf <[email protected]>
Expand Down
13 changes: 13 additions & 0 deletions arch/arm/boot/dts/aspeed-g6.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,11 @@
<0x40466000 0x2000>;
};

ahbc: bus@1e600000 {
compatible = "aspeed,ast2600-ahbc", "syscon";
reg = <0x1e600000 0x100>;
};

fmc: spi@1e620000 {
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
Expand Down Expand Up @@ -431,6 +436,14 @@
reg = <0x1e6f2000 0x1000>;
};

acry: crypto@1e6fa000 {
compatible = "aspeed,ast2600-acry";
reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;
aspeed,ahbc = <&ahbc>;
};

video: video@1e700000 {
compatible = "aspeed,ast2600-video-engine";
reg = <0x1e700000 0x1000>;
Expand Down
14 changes: 6 additions & 8 deletions arch/arm/crypto/sha1_glue.c
Original file line number Diff line number Diff line change
Expand Up @@ -21,31 +21,29 @@

#include "sha1.h"

asmlinkage void sha1_block_data_order(u32 *digest,
const unsigned char *data, unsigned int rounds);
asmlinkage void sha1_block_data_order(struct sha1_state *digest,
const u8 *data, int rounds);

int sha1_update_arm(struct shash_desc *desc, const u8 *data,
unsigned int len)
{
/* make sure casting to sha1_block_fn() is safe */
/* make sure signature matches sha1_block_fn() */
BUILD_BUG_ON(offsetof(struct sha1_state, state) != 0);

return sha1_base_do_update(desc, data, len,
(sha1_block_fn *)sha1_block_data_order);
return sha1_base_do_update(desc, data, len, sha1_block_data_order);
}
EXPORT_SYMBOL_GPL(sha1_update_arm);

static int sha1_final(struct shash_desc *desc, u8 *out)
{
sha1_base_do_finalize(desc, (sha1_block_fn *)sha1_block_data_order);
sha1_base_do_finalize(desc, sha1_block_data_order);
return sha1_base_finish(desc, out);
}

int sha1_finup_arm(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *out)
{
sha1_base_do_update(desc, data, len,
(sha1_block_fn *)sha1_block_data_order);
sha1_base_do_update(desc, data, len, sha1_block_data_order);
return sha1_final(desc, out);
}
EXPORT_SYMBOL_GPL(sha1_finup_arm);
Expand Down
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