drm/amd/display: Disable OTG for mode timing switch on DCN35

[why] Doing a mode timing change causes a hang when OTG is not disabled. [how] Add link_enc null check in disable_otg_wa to cover this case. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hersen Wu <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
kawasaki · Nov 7, 2023 · 3e18d4b · 3e18d4b
1 parent d0ef62b
commit 3e18d4b
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -124,7 +124,8 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *
 
 		if (pipe->top_pipe || pipe->prev_odm_pipe)
 			continue;
-		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
+		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
+				     !pipe->stream->link_enc)) {
 			struct stream_encoder *stream_enc = pipe->stream_res.stream_enc;
 
 			if (disable) {