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drm/amd/display: add check for PMFW hard min request complete
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[Why]
When we issue hard min request to PMFW, the ack back does not
guarantee the request has been fulfilled.

[How]
Add new PMFW message to check if the hard min request has been
completed. Returned bit mask indicates which clock requests are
completed. Check PMFW version before using message

Reviewed-by: Alvin Lee <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Signed-off-by: Samson Tam <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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@alexdeucher
Samson Tam authored and alexdeucher committed Aug 30, 2023
1 parent a03aa4e commit 5133b8d
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Showing 2 changed files with 162 additions and 3 deletions.
11 changes: 10 additions & 1 deletion drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dalsmc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,16 @@
#define DALSMC_MSG_SetFclkSwitchAllow 0x11
#define DALSMC_MSG_SetCabForUclkPstate 0x12
#define DALSMC_MSG_SetWorstCaseUclkLatency 0x13
#define DALSMC_Message_Count 0x14
#define DALSMC_MSG_SetAlwaysWaitDmcubResp 0x14
#define DALSMC_MSG_ReturnHardMinStatus 0x15
#define DALSMC_Message_Count 0x16

#define CHECK_HARD_MIN_CLK_DISPCLK 0x1
#define CHECK_HARD_MIN_CLK_DPPCLK 0x2
#define CHECK_HARD_MIN_CLK_DPREFCLK 0x4
#define CHECK_HARD_MIN_CLK_DCFCLK 0x8
#define CHECK_HARD_MIN_CLK_DTBCLK 0x10
#define CHECK_HARD_MIN_CLK_UCLK 0x20

typedef enum {
FCLK_SWITCH_DISALLOW,
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154 changes: 152 additions & 2 deletions drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,64 @@ static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint
return false;
}

/*
* Use these functions to return back delay information so we can aggregate the total
* delay when requesting hardmin clk
*
* dcn32_smu_wait_for_response_delay
* dcn32_smu_send_msg_with_param_delay
*
*/
static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)
{
uint32_t reg = 0;
*total_delay_us = 0;

do {
reg = REG_READ(DAL_RESP_REG);
if (reg)
break;

if (delay_us >= 1000)
msleep(delay_us/1000);
else if (delay_us > 0)
udelay(delay_us);
*total_delay_us += delay_us;
} while (max_retries--);

return reg;
}

static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)
{
unsigned int delay1_us, delay2_us;
*total_delay_us = 0;

/* Wait for response register to be ready */
dcn32_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay1_us);

/* Clear response register */
REG_WRITE(DAL_RESP_REG, 0);

/* Set the parameter register for the SMU message */
REG_WRITE(DAL_ARG_REG, param_in);

/* Trigger the message transaction by writing the message ID */
REG_WRITE(DAL_MSG_REG, msg_id);

/* Wait for response */
if (dcn32_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay2_us) == DALSMC_Result_OK) {
if (param_out)
*param_out = REG_READ(DAL_ARG_REG);

*total_delay_us = delay1_us + delay2_us;
return true;
}

*total_delay_us = delay1_us + 2000000;
return false;
}

void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)
{
smu_print("FCLK P-state support value is : %d\n", enable);
Expand Down Expand Up @@ -122,20 +180,112 @@ void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
DALSMC_MSG_BacoAudioD3PME, 0, NULL);
}

/* Check PMFW version if it supports ReturnHardMinStatus message */
static bool dcn32_get_hard_min_status_supported(struct clk_mgr_internal *clk_mgr)
{
if (ASICREV_IS_GC_11_0_0(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
if (clk_mgr->smu_ver >= 0x4e6a00)
return true;
} else if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
if (clk_mgr->smu_ver >= 0x524e00)
return true;
} else { /* ASICREV_IS_GC_11_0_3 */
if (clk_mgr->smu_ver >= 0x503900)
return true;
}
return false;
}

/* Returns the clocks which were fulfilled by the DAL hard min arbiter in PMFW */
static unsigned int dcn32_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)
{
uint32_t response = 0;

/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
uint32_t param = 0;

*no_timeout = dcn32_smu_send_msg_with_param_delay(clk_mgr,
DALSMC_MSG_ReturnHardMinStatus, param, &response, total_delay_us);

smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n",
*no_timeout, *total_delay_us, response);

return response;
}

static bool dcn32_smu_wait_get_hard_min_status(struct clk_mgr_internal *clk_mgr,
uint32_t clk)
{
int readDalHardMinClkBits, checkDalHardMinClkBits;
unsigned int total_delay_us, read_total_delay_us;
bool no_timeout, hard_min_done;

static unsigned int cur_wait_get_hard_min_max_us;
static unsigned int cur_wait_get_hard_min_max_timeouts;

checkDalHardMinClkBits = CHECK_HARD_MIN_CLK_DPREFCLK;
if (clk == PPCLK_DISPCLK)
checkDalHardMinClkBits |= CHECK_HARD_MIN_CLK_DISPCLK;
if (clk == PPCLK_DPPCLK)
checkDalHardMinClkBits |= CHECK_HARD_MIN_CLK_DPPCLK;
if (clk == PPCLK_DCFCLK)
checkDalHardMinClkBits |= CHECK_HARD_MIN_CLK_DCFCLK;
if (clk == PPCLK_DTBCLK)
checkDalHardMinClkBits |= CHECK_HARD_MIN_CLK_DTBCLK;
if (clk == PPCLK_UCLK)
checkDalHardMinClkBits |= CHECK_HARD_MIN_CLK_UCLK;

if (checkDalHardMinClkBits == CHECK_HARD_MIN_CLK_DPREFCLK)
return 0;

total_delay_us = 0;
hard_min_done = false;
while (1) {
readDalHardMinClkBits = dcn32_smu_get_hard_min_status(clk_mgr, &no_timeout, &read_total_delay_us);
total_delay_us += read_total_delay_us;
if (checkDalHardMinClkBits == (readDalHardMinClkBits & checkDalHardMinClkBits)) {
hard_min_done = true;
break;
}


if (total_delay_us >= 2000000) {
cur_wait_get_hard_min_max_timeouts++;
smu_print("SMU Wait get hard min status: %d timeouts\n", cur_wait_get_hard_min_max_timeouts);
break;
}
msleep(1);
total_delay_us += 1000;
}

if (total_delay_us > cur_wait_get_hard_min_max_us)
cur_wait_get_hard_min_max_us = total_delay_us;

smu_print("SMU Wait get hard min status: no_timeout %d, delay %d us, max %d us, read %x, check %x\n",
no_timeout, total_delay_us, cur_wait_get_hard_min_max_us, readDalHardMinClkBits, checkDalHardMinClkBits);

return hard_min_done;
}

/* Returns the actual frequency that was set in MHz, 0 on failure */
unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
{
uint32_t response = 0;
bool hard_min_done = false;

/* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
uint32_t param = (clk << 16) | freq_mhz;

smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);

dcn32_smu_send_msg_with_param(clk_mgr,
DALSMC_MSG_SetHardMinByFreq, param, &response);
DALSMC_MSG_SetHardMinByFreq, param, &response);

smu_print("SMU Frequency set = %d KHz\n", response);
if (dcn32_get_hard_min_status_supported(clk_mgr)) {
hard_min_done = dcn32_smu_wait_get_hard_min_status(clk_mgr, clk);
smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done);
} else
smu_print("SMU Frequency set = %d KHz\n", response);

return response;
}
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