riscv: fix misalgned trap vector base address

The trap vector marked by label .Lsecondary_park must align on a
4-byte boundary, as the {m,s}tvec is defined to require 4-byte
alignment.

Signed-off-by: Chen Lu <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Fixes: e011995 ("RISC-V: Move relocate and few other functions out of __init")
Cc: [email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

arch/riscv/kernel/head.S

@@ -193,6 +193,7 @@ setup_trap_vector:
 	csrw CSR_SCRATCH, zero
 	ret
 
+.align 2
 .Lsecondary_park:
 	/* We lack SMP support or have too many harts, so park this hart */
 	wfi