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drm/amd/display: Enable runtime register offset init for DCN32 DMUB
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[Why&How]
DMUB subsystem was continuing to use compile time offset calculation for
register access. Switch this to runtime calculation to stay consistent
with rest of DC code.

To enable this, an additional interface init_reg_offsets() are added to
DMUB's hw_funcs struct. Asics with runtime register offset calculation
enabled shall populate this hook with a fn pointer that will invoke the
necessary macros to calculate the offset.

Reviewed-by: Alvin Lee <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Signed-off-by: Aurabindo Pillai <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Aurabindo Pillai authored and alexdeucher committed Aug 30, 2023
1 parent 45f98fc commit 96182df
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Showing 5 changed files with 36 additions and 20 deletions.
5 changes: 5 additions & 0 deletions drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Original file line number Diff line number Diff line change
Expand Up @@ -1069,6 +1069,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
struct abm *abm = adev->dm.dc->res_pool->abm;
struct dc_context *ctx = adev->dm.dc->ctx;
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
const unsigned char *fw_inst_const, *fw_bss_data;
Expand All @@ -1090,6 +1091,10 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
return -EINVAL;
}

/* initialize register offsets for ASICs with runtime initialization available */
if (dmub_srv->hw_funcs.init_reg_offsets)
dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);

status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
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4 changes: 3 additions & 1 deletion drivers/gpu/drm/amd/display/dmub/dmub_srv.h
Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,7 @@
*/

#include "inc/dmub_cmd.h"
#include "dc/dc_types.h"

#if defined(__cplusplus)
extern "C" {
Expand Down Expand Up @@ -399,6 +400,7 @@ struct dmub_srv_hw_funcs {
void (*get_diagnostic_data)(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);

bool (*should_detect)(struct dmub_srv *dmub);
void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);
};

/**
Expand Down Expand Up @@ -438,7 +440,7 @@ struct dmub_srv {
/* private: internal use only */
const struct dmub_srv_common_regs *regs;
const struct dmub_srv_dcn31_regs *regs_dcn31;
const struct dmub_srv_dcn32_regs *regs_dcn32;
struct dmub_srv_dcn32_regs *regs_dcn32;

struct dmub_srv_base_funcs funcs;
struct dmub_srv_hw_funcs hw_funcs;
Expand Down
34 changes: 20 additions & 14 deletions drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
Original file line number Diff line number Diff line change
Expand Up @@ -26,33 +26,39 @@
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn32.h"
#include "dc/dc_types.h"

#include "dcn/dcn_3_2_0_offset.h"
#include "dcn/dcn_3_2_0_sh_mask.h"

#define DCN_BASE__INST0_SEG2 0x000034C0

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
#define CTX dmub
#define REGS dmub->regs_dcn32
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
{
DMUB_DCN32_REGS()
DMCUB_INTERNAL_REGS()
},
#define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
{
struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32;

#define REG_STRUCT regs

#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
DMUB_DCN32_REGS()
DMCUB_INTERNAL_REGS()
#undef DMUB_SR

#define DMUB_SF(reg, field) FD_MASK(reg, field),
{ DMUB_DCN32_FIELDS() },
#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
DMUB_DCN32_FIELDS()
#undef DMUB_SF

#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
{ DMUB_DCN32_FIELDS() },
#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
DMUB_DCN32_FIELDS()
#undef DMUB_SF
};

#undef REG_STRUCT
}

static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
uint64_t *fb_base,
Expand Down
10 changes: 5 additions & 5 deletions drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
Original file line number Diff line number Diff line change
Expand Up @@ -178,13 +178,11 @@ struct dmub_srv_dcn32_reg_mask {
};

struct dmub_srv_dcn32_regs {
const struct dmub_srv_dcn32_reg_offset offset;
const struct dmub_srv_dcn32_reg_mask mask;
const struct dmub_srv_dcn32_reg_shift shift;
struct dmub_srv_dcn32_reg_offset offset;
struct dmub_srv_dcn32_reg_mask mask;
struct dmub_srv_dcn32_reg_shift shift;
};

extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;

void dmub_dcn32_reset(struct dmub_srv *dmub);

void dmub_dcn32_reset_release(struct dmub_srv *dmub);
Expand Down Expand Up @@ -256,4 +254,6 @@ void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_re
void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);
uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

#endif /* _DMUB_DCN32_H_ */
3 changes: 3 additions & 0 deletions drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
Original file line number Diff line number Diff line change
Expand Up @@ -78,6 +78,8 @@

#define DMUB_REGION5_BASE (0xA0000000)

static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;

static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
{
return (val + factor - 1) / factor * factor;
Expand Down Expand Up @@ -304,6 +306,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
funcs->get_current_time = dmub_dcn32_get_current_time;
funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
funcs->init_reg_offsets = dmub_srv_dcn32_regs_init;

break;

Expand Down

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